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    3,240 verilog vhdl 仕事が見つかりました。次の価格: USD
    Verilog/VHDL task 6 日 left
    認証完了

    Hello freelancers. I have some works related to Verilog/VHDL and i am looking for someone who can work with me for a long term. I need someone who can handle simple as well as complex tasks. I will share details of work with selected freelancer.

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    5 入札

    I need help in doing record for VHDL code and write the observations from the code. Code is working good but need help writing the observations from it. VHDL and De2-115 board

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    PWM vhdl fpga 3 日 left

    Description is in attached file. Note: Text is in Bosnian language so you will need to translate it.

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    I have a matlab test file along with some function files. Need to convert them into VHDL.

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    I would need VHDL code for an integer divider; thorough and detailed specifications will be provided after project acceptance. My timeline is quite strict (end is next Monday 13th); moreover I will need to contact the Developer for clarifications and explanation of coding choices (in the following weeks). This is needed because I must understand how the code works (and am a beginner with VHDL).

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    VHDL expert 終了 left

    i am looking for an expert in VHDL

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    build CNN using MAC unit in verilog to trian it using MNIST data set

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    8 入札

    I have a lot of works related to different fields of electrical engineering looking for experts in following areas: • Embedded C Programming. • VHDL/Verilog • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • Multisim • IOT Technologies...

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    We are from an IT project consultant and an online tutoring company also One of our client is looking for Verilog Project Assistance

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    I need a ZIP file including: – a report in PDF following an IEEE paper format – a folder with VHDL codes (at least 2 VHDL files are expected) – a TCL script and a file [ログインしてURLを表示] – Use QuestaSim/ModelSim as the simulator tool The primary goal of this job is to report the design and the validation of a 3D printer machine implemented in VHDL. The underlying 3D printer ...

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    I need a ZIP file including: – a report in PDF following an IEEE paper format – a folder with VHDL codes (at least 2 VHDL files are expected) – a TCL script and a file [ログインしてURLを表示] – Use QuestaSim/ModelSim as the simulator tool The primary goal of this job is to report the design and the validation of a 3D printer machine implemented in VHDL. The underlying 3D printer ...

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    特集 緊急
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    FPGA project using VHDL about sequential logic circuits, details will be provided

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    Designing a digital system and implementing it using system verilog programming language with a basys.

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    8 入札

    Designing a digital system and implementing it using system verilog programming language with a basys.

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    Designing a digital system and implementing it using system verilog programming language with a basys.

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    5 入札

    Designing a digital system and implementing it using system verilog programming language with a basys.

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    15 入札

    Needs 6 hours tutoring for verolog Programing Will discus on chatt Design a structural System Verilog module for a 7 segment display decoder with a four-bit input C, and a seven bit output Y , which can be used to display the character associated with the hexadecimal code represented by C on a 7-segment display on the development board. Instantiate your seven segment decoder module on the develop...

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    I need to finish a VHDL Vending Machine ASAP.

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    Kcpsm6 Picoblaze 8 bit microcontroller xilinx, (FIDEx assembly instruction memory creation) Design 3 PicoBlazes and a Block RAM system. Data in Block RAM will be transfer to PicoBlaze_S1 and PicoBlaze_S2 via PicoBlaze_M. Between there is only 8 bit data bus between Master and Slave processors (only in_port or out_port can be used for each picoblaze). First 8 bit will indicate which slave system wi...

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    Hi ducdctoandh, I need the small paper in ECC implementation in Modelsim first the introduction about algorithm and the verilog and simulation encryption and decryption and timing summary all the in work file with secreen shoot must put my name Yasmin in every file i can send file for other work

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    hi i need to create a vhdl [ログインしてURLを表示] project details are explained in

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    10 入札

    You are required to make a code that takes an input from the user , changes the clock frequency using that input and gives the user 3 guesses to find the changed clock frequency the code is for a Spartan 3A FPGA

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    The goal is to make a project where we have 2 pictures: 1 from ov7670 and 1 from pc, applying green screen effect to the 1st one (the picture will be taken with the green background), changing the green pixels with the 2nd picture and then see it on pc by uart or vga. The codes are needed to be in VHDL. I don't need a great resolution for pictures, 160x120 pictures with 8 bit or 16 bit colors...

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    6 入札
    Verilog program 終了 left

    I need to make an ALU that can make an output using data_in from an tester .. also the data in can be an header on payload acordoing from 2 other signals

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    i need the help of an expert who is very good to help write a VHDL code for a very simple system,i need it urgently, many thanks

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    It is a project to write a VHDL code and implement on a 7 segment display. Attached is complete description of all the requirements

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    O freelancer deverá conhecer as linguagens = C / vhdl / verilog e já ter trabalhado com FPGA / ASIC Portar e otimizar um código que já tenho pronto em "c" para vhdl ou verilog esse código gera uma string de 14 / 15 dígitos, será usado uma placa fpga xillinx spartan 6 ( a empresa xillinx disponibiliza todo o ambiente necessário ). ...

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    SRAM BIST needs to be done in Verilog with synthesis in design compiler and fixing timing violation in prime time

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    You are required to build a calculator: 1- it generates numbers (0-99) on the seven segment display using push buttons. The first 2 digits on the board should be the first number. The second 2 digits should be the second number. 2- using the slide switches you should add, subtract, multiply and divide these 2 numbers. Then display the answer on the fpga board. Write the source code and constrain...

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    You are required to build a calculator: 1- it generates numbers (0-99) on the seven segment display using push buttons. The first 2 digits on the board should be the first number. The second 2 digits should be the second number. 2- using the slide switches you should add, subtract, multiply and divide these 2 numbers. Then display the answer on the fpga board. Write the source code and constrain...

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    9 入札

    Hi, I need help with a Verilog project with synthesis and optimization using Design Compiler and fix the timing violations using Primetime. Could you please let me know if you are interested.

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    Project goal is designing 4x4 binary multiplier with shift & add algorithm. Stricted rules: Project must be prepared with Verilog [Vivado Design Suite] (System Verilog and VHDL is not acceptable) I need circuit design, Verilog models and basic report (Explanation of how things work, schematics, verilog codes etc) If you're interested, I can share detailed pdf of project with you.

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    Budget: CAD $20-30 Time: 1-3 Days Need to design a segment display in VHDL.

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    6 入札

    Hello Experts Looking for good digital electronics expert with knowledge of verilog, fpga , mips etc to work on small project today 9th dec. Apply only if you are available to help today Thanks

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    Hello Experts Looking for good digital electronics expert with knowledge of verilog, fpga , mips etc to work on small project today 9th dec. Apply only if you are available to help today Thanks

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    vhdl coding

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    Hello There Need very good digital electronics based expert to help on small project today ie 9th Dec. If you are good with verilog, FPGA, MIPS etc then apply only. You ll be hired asap if you are sure you'll help today

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    5 入札

    Hello There Need very good digital electronics based expert to help on small project tomorrow ie 9th Dec. If you are good with verilog, FPGA, MIPS etc then apply only. You ll be hired asap if you are available to start on 9th dec Thanks

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    Hi, I am looking for someone who can capture a 16 bit data from input of the picoblaze processor and add some constant value into it and give the result on output. No need to verify on board, only testbench simulation is accepted in VHDL.

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    For this project the goal is to design and simulate a Blackjack game using Verilog/VHDL. It must be demonstrated using the Mimas Spartan 6 FPGA board. The inputs are taken from the player using the switches and push buttons while the output is displayed on the LCD display and LEDs.

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    Hello Need very good digital electronics based expert to help on small project tomorrow ie 9th Dec. If you are good with verilog, FPGA, MIPS etc then apply only. You ll be hired asap if you are available to start on 9th dec Read Less

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    6 入札

    Hello Need very good digital electronics based expert to help on small project tomorrow ie 9th Dec. If you are good with verilog, FPGA, MIPS etc then apply only. You ll be hired asap if you are available to start on 9th dec

    $88 (Avg Bid)
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    3 入札

    Hello Need very good digital electronics based expert to help on small project tomorrow ie 9th Dec. If you are good with verilog, FPGA, MIPS etc then apply only. You ll be hired asap if you are available to start on 9th dec

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    Need VHDL code 終了 left

    Need VHDL code This project consists of two main components. A counter programmed with VHDL and an ALU based on MicroBlaze running a C code to perform ALU functionality. 1. This project requires the students to implement a 10-bit counter design using VHDL. The counter will have the ability to count up and down from 0 and 1000. This requires the utilization of 16 slide switches and the center push ...

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    Hardware implementation of elliptic curve over binary field 163 field , with UART using VHDL and the platform is virtex 5

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    The project here is to write multiple conditions/actions using VHDL format, that can all be displayed in 1 single program. And tested on an Altera DE2 board Port mapping could be okay but using relatively basic principles is ideal. That is (all are not required): Case statements Else / ElseIf Signals Variables Shift register Flip Flops Multiplexer / De-multiplexer Multibit adder A...

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    I need a design implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer (A/P) control RGB LEDs (document attached). Ideally the potentiometer would control the brightness of one of the colors and be able to switch between red, green, or blue. This does not need to actually be programmed onto the board. The schematic, code, and te...

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    I will upload a file explaining the project. It uses AHB's to use ALS and VGA to run a code of a door lock. I have the Verilog codes for the door lock just need to add some functions with the ALS and VGA.

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    VHDL tutor 終了 left

    Hi, I am looking for help with a VHDL project. Project is create a combinational lock system using VHDL. Lock will open when entered passcode is correct and message "O" will be display on LCD. If entered passcode is not correct, then lock will not open and message "L" will be displayed on LCD. If user enters wrong passcode more than 2 times, then RED LED should Blink. VHDL cod...

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