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プロジェクト / コンテスト 詳細 入札 / エントリー スキル 開始日 終了日 価格(JPY)
FPGA chip hardware periphery design Design a small PCB (~20x25mm) around an bear-bone FPGA-chip (XC7A15T-1CPG236C) that is able to configure itself on every power-up from a flash memory that can be also found on the PCB. Also it is necessary to design a programming interface for the flash memory on the PCB as it should be possible to load the bitstream to the flash with an ESP32 module. Writing an XDC file and configuring protocol (... 19 エレクトロニクス, Verilog/ VHDL, 電気工学, PCBレイアウト, FPGA Jan 18, 2018 本日6日 1時間 ¥112548
vhdl help needed Need constraints file edited in order to make the code work. Small work which will only take few minutes. Vhdl experts contact me please 11 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Jan 15, 2018 Jan 15, 20182日 18時間 ¥2543
need an expert on vhdl vhdl expert needed to check on the code 9 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Jan 14, 2018 Jan 14, 20182日 14時間 ¥2038
Project for Constantin R. Hi Constantin R., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 マイクロコントローラ, PCBレイアウト, , Arduino, 回路設計, FPGA Jan 12, 2018 Jan 12, 20183日 3時間 ¥677844
need a VHDL expert asap vhdl expert needed asap to run a code 16 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Jan 10, 2018 Jan 10, 2018終了 ¥2182
verilog code need some help with verilog code. 22 Verilog/ VHDL, ソフトウェアアーキテクチャ, LabVIEW, Assembly, FPGA Jan 9, 2018 Jan 9, 2018終了 ¥1853
License Plate Detection Using VHDL I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code 8 エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Jan 9, 2018 Jan 9, 2018終了 ¥63129
VHDL - SRAM -FPGA This is the project: FSM, saving data blocks received via RS-232 with fixed baud rate in external RAM and extracting necessary byte from arbitrary address (selected by slide-switches). - I need VHDL code and Testbench. -Explain its behavior and parts. I am using ZedBoard ZYNQ SOC training , Xilinx Zynq-7000 9 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Jan 8, 2018 Jan 8, 2018終了 ¥6081
SFP communication with FPGA Coding required for FPGA to SFP communication 13 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Jan 6, 2018 Jan 6, 2018終了 ¥99170
VHDL for programming FPGA board Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. 18 Verilog/ VHDL, FPGA Jan 2, 2018 Jan 2, 2018終了 ¥14041
Work with Digital Electronic and Analogue Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 13 エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Dec 28, 2017 Dec 28, 2017終了 ¥3648
Need an expert in ASIC board - 1 Hello, everyone! I need you to design ASIC board for mining BTC. If you are an expert in this field, please bid this project. We can discuss more details over chat. Thanks in advance. 8 エレクトロニクス, 製造, マイクロコントローラ, 電気工学, FPGA Dec 24, 2017 Dec 24, 2017終了 ¥535876
Convert some VHDL to Verilog Contact me for more details. All I need done is porting some VHDL to Verilog. 18 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, ソフトウェアアーキテクチャ, FPGA Dec 23, 2017 Dec 23, 2017終了 ¥13046
Need an expert in ASIC board Hello, everyone! I need you to design ASIC board for mining BTC. If you are an expert in this field, please bid this project. We can discuss more details over chat. Thanks in advance. 4 エレクトロニクス, 製造, マイクロコントローラ, 電気工学, FPGA Dec 23, 2017 Dec 23, 2017終了 ¥436042
vhdl code using altera Design a digital system that will generate police or unbalance siren sound 9 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Dec 22, 2017 Dec 22, 2017終了 ¥14483
FPGA Project (VHDL floating and real number mathematical operations using Simulink MATLAB) I need a vhdl program allowing FPGA to do aritmetic calculations with real values. For instance summing, substracting, dividing and multiplying 2 real number values as follows: (2.32 + 3.65; 2.32 - 3.65; 2.32/3.65 ; 2.32*3.65) I assume it suppose to be done using some toolbox on MATLAB ( System Generator Toolbox) This code should work on Xilinx Spartan 6. I want the code written simp... 10 Matlab and Mathematica, Verilog/ VHDL, 電気工学, LabVIEW, FPGA Dec 21, 2017 Dec 21, 2017終了 ¥7186
Microcontroller design Design and implementation of controller with VHDL in FPGA 13 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, FPGA Dec 19, 2017 Dec 19, 2017終了 ¥15718
Generate GPS signal using verilog In my project , I have to generate gps signal using verilog code. For this I need C/A code, random data, carrier signal. So first I have to do bpsk to random data and c/a code then do bpsk with carrier signal . I have given you c/a code you have generate random data , carrier signal and give me output code as well as pictures within 1 or 2 days. 1 Verilog/ VHDL, 電気工学, FPGA Dec 19, 2017 本日終了 ¥3886
Multi-Core ASIC Design - SHA256 Looking for competent person to aide in design of algorithm & ASIC design for cryptocurrency. 8 FPGA Dec 18, 2017 本日終了 ¥27861
Simple Verilog code Write a simple verilog code to create dynamic lighting using led. see the attached files and respond 26 C プログラミング, Verilog/ VHDL, マイクロコントローラ, LabVIEW, FPGA Dec 15, 2017 Dec 15, 2017終了 ¥13599
help me with modify some Verilog code know Verilog code, how how to use Quartus and FPGA board. 16 Verilog/ VHDL, マイクロコントローラ, 電気工学, LabVIEW, FPGA Dec 15, 2017 Dec 15, 2017終了 ¥2653
Create an ASIC board capable of hasing SHA256 (2-20Th/s) Good Day I am interested in finding somebody who will be able to design an ASIC board for my team and I. It needs to be able to hash SHA256 in order to mine bitcoin. It is up to you to decide whether you will be using FPGAs or other off-the-shelf ICCs. You will be working with some of the greatest experts in manufacturing and bussiness. It must meet or surpass the following specifications: ... 5 エレクトロニクス, マイクロコントローラ, 電気工学, 回路設計, FPGA Dec 14, 2017 Dec 14, 2017終了 ¥40062576
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Dec 11, 2017 Dec 11, 2017終了 ¥2543
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Dec 9, 2017 Dec 9, 2017終了 ¥6081
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Dec 9, 2017 Dec 9, 2017終了 -
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 11 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Dec 8, 2017 Dec 8, 2017終了 ¥49421
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Dec 7, 2017 Dec 7, 2017終了 ¥86884
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 回路設計, FPGA Dec 2, 2017 Dec 2, 2017終了 ¥4975
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 C プログラミング, Verilog/ VHDL, C++プログラミング, Assembly, FPGA Nov 30, 2017 Nov 30, 2017終了 ¥17358
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog/ VHDL, FPGA Nov 29, 2017 Nov 29, 2017終了 ¥9176
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 C プログラミング, エンジニアリング, Verilog/ VHDL, FPGA, Parallel Processing Nov 29, 2017 Nov 29, 2017終了 ¥19016
embedded s Project: The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single... 2 FPGA Nov 28, 2017 Nov 28, 2017終了 ¥7960
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 エンジニアリング, Verilog/ VHDL, 電気工学, ネットワーク管理, FPGA Nov 26, 2017 Nov 26, 2017終了 ¥74627
SOC integration problem About timing violation at cross clock domain 1 FPGA Nov 26, 2017 Nov 26, 2017終了 ¥2764
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 C プログラミング, Verilog/ VHDL, C#プログラミング, C++プログラミング, FPGA Nov 23, 2017 Nov 23, 2017終了 ¥1177
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 C プログラミング, Verilog/ VHDL, C++プログラミング, Assembly, FPGA Nov 23, 2017 Nov 23, 2017終了 ¥1106
System Verliog task available I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer 8 エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Nov 22, 2017 Nov 22, 2017終了 ¥2610
Computer Design and ProtoTyping build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit s... 8 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Nov 22, 2017 Nov 22, 2017終了 ¥19569
VHDL coding needed to be done by expert!! VHDL coding needed to be done by expert!! $30 CAD pay 8 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Nov 22, 2017 Nov 22, 2017終了 ¥2435
LabWindows/CVI Project Simple Update.(send emails when yields goes down) - open to bidding I need a little update in my Test Program (Labwindows). All code and GUI and all is done, just need program be capable to send email automatically to specified people when yields goes down <97%. 4 C プログラミング, エンジニアリング, C#プログラミング, 組み込みソフト, FPGA Nov 21, 2017 Nov 21, 2017終了 ¥18463
UVM verification of memory controller - open to bidding Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified. 5 パール, Verilog/ VHDL, シェルスクリプト, FPGA, Very-large-scale integration (VLSI) Nov 21, 2017 Nov 21, 2017終了 ¥41459
SMC Interface and SPI Slave Logic for CPLD Project 1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic 7 C プログラミング, エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, FPGA Nov 21, 2017 Nov 21, 2017終了 ¥3096
Video transmission system and USB emulator Project for huge experienced engineers. Result: Altium project and firmware. Details of the project in the attachment. 4 エレクトロニクス, Verilog/ VHDL, PCBレイアウト, FPGA Nov 20, 2017 Nov 20, 2017終了 ¥155777
VHDL task URGENT Please check the attachment for the details Need to use Quartus ll 10 エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Nov 18, 2017 本日終了 ¥4975
FPGA implementation of three phase locked loop i want to implement three phase locked loop implemented in simulink 20 エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Nov 18, 2017 Nov 18, 2017終了 ¥53842
FPGA and DSP develper Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs. 16 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Nov 17, 2017 Nov 17, 2017終了 ¥6191
implement one project with system verilog in Zynq I need to implement the threshold block and verify that with two AXI VIP as you can see in the picture. I need a testbench which generates random numbers between 500 to 1000 and the threshold block count the number of data more than 500. the project can be done also with ILA but at this point I prefer system Verilog. Xilinx has a tesbecnh example which helps to write a code quickly. 4 Verilog/ VHDL, 電気工学, FPGA Nov 9, 2017 Nov 9, 2017終了 ¥10518
vhdl code using xilinx vhdl code using xilinx and simulate it using isim 14.7 7 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Nov 7, 2017 Nov 7, 2017終了 ¥3538
FPGA Project Detail will be given in contact. 19 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Nov 7, 2017 Nov 7, 2017終了 ¥19127
Project for Pradeep S. Hi Pradeep S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 パイソン, マイクロコントローラ, , Arduino, FPGA, Raspberry Pi Nov 1, 2017 Nov 1, 2017終了 ¥1769
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