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プロジェクト / コンテスト 詳細 入札 / エントリー スキル 開始日 終了日 価格(JPY)
Sending and receiving tcpip xgmii packets over SFP+ This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server. 1 Verilog/ VHDL, FPGA Apr 19, 2018 本日6日 22時間 ¥59543
Create a DLX Data Path Using VHDL Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. 6 Verilog/ VHDL, マイクロコントローラ, ソフトウェアアーキテクチャ, Assembly, FPGA Apr 18, 2018 本日6日 6時間 ¥20170
Do VHDL project on the ModelSim I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... 10 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Apr 18, 2018 Apr 18, 20185日 19時間 ¥17166
verilog expert only more details will be given in the chat 15 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Apr 18, 2018 Apr 18, 20185日 16時間 ¥1959
SoundLocator Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position 14 Java, エレクトロニクス, Android, Verilog/ VHDL, FPGA Apr 18, 2018 Apr 18, 20185日 16時間 ¥66411
Serializer & Desrializer Implementation using ZC706 and MTX Serializer & Desrializer Implementation using ZC706 and MTX 6 Verilog/ VHDL, FPGA Apr 17, 2018 Apr 17, 20185日 8時間 ¥3111
OpenCL FPGA Code modification I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [URLが削除済みです、ログインして表示してください] Please respond directly with any questions such as specific mining software and such. 8 C プログラミング, Verilog/ VHDL, 暗号化, オープンCL, FPGA Apr 17, 2018 Apr 17, 20185日 3時間 ¥248042
expert in vivado vhdl needed expert in vivado and vhdl needed asap 8 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Apr 17, 2018 Apr 17, 20184日 20時間 ¥2701
Logisim Digital Logic Design using four bit ALU, given two numbers A and B we need to find if A is divisible by B 14 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Apr 17, 2018 Apr 17, 20184日 16時間 ¥8690
Neural Network on an FPGA I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. 4 C プログラミング, Verilog/ VHDL, 機械学習, FPGA, Neural Networks Apr 17, 2018 Apr 17, 20184日 10時間 ¥18615
VHDL digital lock I have a project that im working on and need to do it by 4/27/2018. I need to show the simulation that the program is running and may need help understanding how it runs. I want someone to do the project and explain to me how it was done and to show me that the program is running (simulation). I have attached a file of the description and the board I will be using, it has and integrated ADC chip ... 17 Verilog/ VHDL, マイクロコントローラ, デジタルデザイン, FPGA Apr 15, 2018 Apr 15, 20183日 6時間 ¥15771
CRYPTO MINING using VHDL in FPGA Details later.. I will check your BASIC.. And then recruit You 3 Verilog/ VHDL, 鉱山学, デジタルデザイン, FPGA Apr 15, 2018 Apr 15, 20182日 23時間 ¥238386
Need a MC6803 replaced with FPGA Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. [URLが削除済みです、ログインして表示してください] . will need relevant information to program multiple devices. 5 FPGA Apr 10, 2018 Apr 10, 2018終了 ¥4828
Serial Interface using Python Design a serial interface using Python for communication with FPGA. 5 パイソン, Verilog/ VHDL, ユーザーインタフェース/IA, ソフトウェアアーキテクチャ, FPGA Apr 2, 2018 Apr 2, 2018終了 ¥3424
parallel multiply simulation -vhdl I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture. 13 C プログラミング, エンジニアリング, Verilog/ VHDL, マイクロコントローラ, FPGA Mar 29, 2018 Mar 29, 2018終了 ¥3540
Electronic Systems - Mode B - Expert I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you 16 エレクトロニクス, マイクロコントローラ, PCBレイアウト, 回路設計, FPGA Mar 29, 2018 Mar 29, 2018終了 ¥65229
JESD204B ADS54J20 vc707. - open to bidding I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat. 6 エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, マイクロコントローラ, FPGA Mar 28, 2018 Mar 28, 2018終了 ¥77352
Custom Arduino Pro Mini PCB layout Is it possible to make an custom made Arduino Pro Mini PCB? It needed to be made trough easyeda pcb and components from 1206 package Remove all holes traces that are x out. Remove reset button ? It needed to be programmable by and FTDI1232 programmer as regular arduino pro It also needed to added some other components to the board.I have a template that needed to be edited on easyeda, that y... 7 マイクロコントローラ, PCBレイアウト, Arduino, 回路設計, FPGA Mar 28, 2018 Mar 28, 2018終了 ¥5042
Absorption Chiller - open to bidding I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work 4 Matlab and Mathematica, Verilog/ VHDL, アルゴリズム, マイクロコントローラ, FPGA Mar 27, 2018 Mar 27, 2018終了 ¥5406
Embedded Systems use quartus compiler/simulator to design a [URLが削除済みです、ログインして表示してください] displays left 16 bits of the result in hexadecimal format...................................................... 6 C プログラミング, Verilog/ VHDL, マイクロコントローラ, C++プログラミング, FPGA Mar 26, 2018 Mar 26, 2018終了 ¥3433
Digital Alarm clock "verilog " I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details 13 Verilog/ VHDL, Assembly, FPGA Mar 23, 2018 Mar 23, 2018終了 ¥6115
expert in simulink and vhdl needed I need an expert in simulink and vhdl 6 エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA Mar 23, 2018 Mar 23, 2018終了 ¥2312
FPGA NIST5 Cryptocurrency miner I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series 6 Verilog/ VHDL, FPGA Mar 23, 2018 Mar 23, 2018終了 ¥79391
Design a Video codec H.264 Processor for Face recognition using Artificial intelligence algorith. Hi This is my research project. i want to design a video codec h.264 processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorith... 2 C プログラミング, エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, FPGA Mar 23, 2018 Mar 23, 2018終了 ¥11516
Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Mar 18, 2018 本日終了
Academic writing I need someone who is expert in academic writing and EE engineering communication and radar field and also embedded systems FPGA, the page's number will be around 50, and the topic and results and design are ready just need to be written. 42 テクニカルライティング, 電気工学, 研究の執筆, FPGA Mar 15, 2018 Mar 15, 2018終了 ¥13518
test_audi in vivado sdk this is my problem : " 'XPAR_AXI_GPIO_0_BASEADDR' undeclared (first use in this function)" 2 FPGA Mar 14, 2018 Mar 14, 2018終了 ¥2897
stepper motor controller A stepper motor controller in verilog , 15 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Mar 11, 2018 Mar 11, 2018終了 ¥20402
vhdl expert needed2 Expert in VHDL is needed to do a project 9 エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, FPGA Mar 3, 2018 Mar 3, 2018終了 ¥2604
FPGA-eMMC interface Design and develop a interface logic for reading and writing to and from eMMC device to support 300Mbps data rate to Video encoder. - timelines - 2-3 weeks. 3 C プログラミング, エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, FPGA Mar 1, 2018 Mar 1, 2018終了 ¥39019
vhdl or verilog project autoamate a door handle using vhdl or verilog 26 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Feb 27, 2018 Feb 27, 2018終了 ¥11372
Add serial connection to verilog project I have some existing code but need to add a serial connection to the hardware. More details to be provided. 15 C プログラミング, Verilog/ VHDL, マイクロコントローラ, ソフトウェアアーキテクチャ, FPGA Feb 27, 2018 Feb 27, 2018終了 ¥6866
Implement RSA algorithm synthesized code (512 bit) in Verilog Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont... 9 エンジニアリング, Verilog/ VHDL, FPGA Feb 24, 2018 Feb 24, 2018終了 ¥11462
DDR3 memory controller interface using nexys video for read write multiple images We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board. 6 C プログラミング, Verilog/ VHDL, マイクロコントローラ, 組み込みソフト, FPGA Feb 21, 2018 Feb 21, 2018終了 ¥18024
Verilog Servo controller I'm looking for someone who can write me a verilog HDL code for a servo controller 7 C プログラミング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Feb 18, 2018 本日終了 ¥3004
An expert in FPGA is required I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 4 C プログラミング, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Feb 12, 2018 Feb 12, 2018終了 ¥16025
FPGA QAR Project I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA. 14 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Feb 12, 2018 Feb 12, 2018終了 ¥52804
FPGA CONSOLE I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 C プログラミング, エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, FPGA Feb 11, 2018 Feb 11, 2018終了 ¥2189
Use edaplayground to run a carry lookahead adder need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works 11 C プログラミング, Verilog/ VHDL, マイクロコントローラ, ソフトウェアアーキテクチャ, FPGA Feb 8, 2018 Feb 8, 2018終了 ¥2575
FIR Filter Reference Design in Verilog We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers 5 Verilog/ VHDL, FPGA Feb 4, 2018 Feb 4, 2018終了 ¥23617
Petalinux on ZC706 I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features. 1 Verilog/ VHDL, FPGA Jan 29, 2018 Jan 29, 2018終了 ¥17809
Project for Constantin R. Hi Constantin R., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 マイクロコントローラ, PCBレイアウト, , Arduino, 回路設計, FPGA Jan 12, 2018 Jan 12, 2018終了 ¥657773
SFP communication with FPGA Coding required for FPGA to SFP communication 13 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA Jan 6, 2018 Jan 6, 2018終了 ¥96233
VHDL for programming FPGA board Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. 18 Verilog/ VHDL, FPGA Jan 2, 2018 Jan 2, 2018終了 ¥13625
Convert some VHDL to Verilog Contact me for more details. All I need done is porting some VHDL to Verilog. 18 エンジニアリング, Verilog/ VHDL, マイクロコントローラ, ソフトウェアアーキテクチャ, FPGA Dec 23, 2017 Dec 23, 2017終了 ¥12660
Need an expert in ASIC board Hello, everyone! I need you to design ASIC board for mining BTC. If you are an expert in this field, please bid this project. We can discuss more details over chat. Thanks in advance. 4 エレクトロニクス, 製造, マイクロコントローラ, 電気工学, FPGA Dec 23, 2017 Dec 23, 2017終了 ¥423131
FPGA Project (VHDL floating and real number mathematical operations using Simulink MATLAB) I need a vhdl program allowing FPGA to do aritmetic calculations with real values. For instance summing, substracting, dividing and multiplying 2 real number values as follows: (2.32 + 3.65; 2.32 - 3.65; 2.32/3.65 ; 2.32*3.65) I assume it suppose to be done using some toolbox on MATLAB ( System Generator Toolbox) This code should work on Xilinx Spartan 6. I want the code written simp... 10 Matlab and Mathematica, Verilog/ VHDL, 電気工学, LabVIEW, FPGA Dec 21, 2017 Dec 21, 2017終了 ¥6974
Microcontroller design Design and implementation of controller with VHDL in FPGA 13 エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, FPGA Dec 19, 2017 本日終了 ¥15252
Generate GPS signal using verilog In my project , I have to generate gps signal using verilog code. For this I need C/A code, random data, carrier signal. So first I have to do bpsk to random data and c/a code then do bpsk with carrier signal . I have given you c/a code you have generate random data , carrier signal and give me output code as well as pictures within 1 or 2 days. 1 Verilog/ VHDL, 電気工学, FPGA Dec 19, 2017 本日終了 ¥3771
Multi-Core ASIC Design - SHA256 Looking for competent person to aide in design of algorithm & ASIC design for cryptocurrency. 8 FPGA Dec 18, 2017 本日終了 ¥27036
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