Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designersを採用する

絞り込む

私の最近の検索
次の条件で絞り込む:
予算
to
to
to
種類
スキル
言語
    ジョブステータス
    16 仕事が見つかりました。次の価格: USD

    Hello Everyone I am looking for an Engineer with sound knowledge of CODESYS for completion of project. More details will be shared with experienced and interested freelancers. The person must have sound knowledge of technical writing as well to handle the description part of the project. Kindly place your competitive bids for further discussion.

    $90 (Avg Bid)
    $90 平均入札額
    8 入札

    a) Derive an expression as a function of W/L for the “on-resistance” of an NMOS switch with the gate tied to V_DD . (Note: Neglect the body effect.) Use a V_DD = 1.8 V and V_t = 500 mV. b) Using Cadence, sweep V_DS from -V_DD /2 to V_DD /2 and W/L with V_G = V_DD and V_S = V_DD/2. The body should be tied to V_SS and L = 500 nm. Show schematic and simulation results. c) Repeat (a) - (b)...

    $110 (Avg Bid)
    $110 平均入札額
    3 入札

    Project Description: 2-Stage Project with 2 milestone payments. 1. The 1st stage is completion of the board design (must use Orcad/Cadence software), which includes schematic, printed circuit board and Bills Of Materials. 1st milestone payment on successful completion of 1st stage 2. The 2nd stage is coding the software with good documentation and 2nd milestone payment is made on successful c...

    $582 (Avg Bid)
    $582 平均入札額
    45 入札

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

    $3823 (Avg Bid)
    $3823 平均入札額
    17 入札
    ADC in FPGA 4 日 left
    認証完了

    Implementation of suitable RC filter for ADC. Digital part implementation is done on FPGA. RC filter has to be designed for given specification.

    $23 (Avg Bid)
    $23 平均入札額
    6 入札

    VHDL code of optimization algorithm fixing.

    $61 (Avg Bid)
    $61 平均入札額
    8 入札

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $167 (Avg Bid)
    $167 平均入札額
    3 入札

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $27 (Avg Bid)
    $27 平均入札額
    1 入札

    i want to design step by step antenna by CST program (spiral antenna) by TeamViewer you will describe to me how to design it

    $120 (Avg Bid)
    $120 平均入札額
    13 入札

    Hi I am looking to hire some expert to implement a pipelined MIPS proccessor simulator in C++ .I will review your bid later so feel free to drop your bid here. The maximum I can offer is 35 CAD !!

    $169 (Avg Bid)
    $169 平均入札額
    3 入札

    Hello Please check it carefully. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ......................................................... [ログインしてURLを表示] have a look here, at the moment I need only labaa 3. maybe you have to download the files because on dr...

    $23 (Avg Bid)
    $23 平均入札額
    2 入札

    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

    $269 (Avg Bid)
    $269 平均入札額
    3 入札
    Operating System Computer Engineer 1 日 left
    認証完了

    need an operation system engineer to help in mathematical CPU process

    $160 (Avg Bid)
    $160 平均入札額
    7 入札

    Program the Odrive motor controller hardware, to make two odrive control four motors, four motor RPM can send to my stm32 microprocessor over can bus.

    $20 / hr (Avg Bid)
    $20 / hr 平均入札額
    11 入札
    $35 平均入札額
    7 入札