Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designersを採用する

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    15 仕事が見つかりました。次の価格: USD

    -Tools:Altera Quartus,Modelsim and FPGA. -This Project is divided to two parts:- [ログインしてURLを表示] and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x 32) 2- ALU 3- Instruction Register 4- Contr...

    $351 (Avg Bid)
    $351 平均入札額
    4 入札
    VLSI Expert 5 日 left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    $250 (Avg Bid)
    $250 平均入札額
    1 入札
    VLSI Project -- 2 4 日 left
    認証完了

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [ログインしてURLを表示]

    $240 (Avg Bid)
    $240 平均入札額
    1 入札

    SIMULINK simulation for BLDC sensorless control using BEMF method

    $40 (Avg Bid)
    $40 平均入札額
    1 入札
    A vlsi design 4 日 left

    magic design on ubuntu where you can build

    $26 (Avg Bid)
    $26 平均入札額
    1 入札
    VLSI Project 3 日 left
    認証完了

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [ログインしてURLを表示]

    $236 (Avg Bid)
    $236 平均入札額
    3 入札

    I need an expert who has excellent knowledge of Microprocessor and Operating System

    $61 (Avg Bid)
    $61 平均入札額
    4 入札

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $47 (Avg Bid)
    $47 平均入札額
    5 入札

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting and growing Blockchain Technology + No cont...

    $15 / hr (Avg Bid)
    $15 / hr 平均入札額
    10 入札
    Vivado HLS Expert 1 日 left
    認証完了

    I am willing to pay for only Vivado HLS expert. Will discuss via interview.

    $1345 (Avg Bid)
    $1345 平均入札額
    8 入札

    The project requires hardware & software design, implementation and testing of a simple & basic multi-function digital clock using Zynq 7000 ZED board. See attached for further information and specifications.

    $425 (Avg Bid)
    $425 平均入札額
    13 入札
    mips assembley langayge project 1 日 left
    認証完了

    i need to build a Gaussian elimination by MIPS

    $53 (Avg Bid)
    $53 平均入札額
    13 入札

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

    $547 (Avg Bid)
    $547 平均入札額
    5 入札

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    $104 (Avg Bid)
    $104 平均入札額
    4 入札