I need you to design a basic processor that performs the basic operations (addition, subtraction, division, multiplication) with the software "Proteus 8.8".
Requiero que me realizen el diseño de un procesador basico que realize las operaciones aritmeticas basicas (suma,resta,division,multiplicacion) con el software de "Proteus 8.8".
I want to implement on NetFPGA SUME board. I post my pre report below.
The objective of this project is to write a Verilog 100MHz SDRAM DDR controller. The controller shall run on a Lattice LCMXO3L-4300E-6MG121I connected to a Winbond 256MBit 16-bit W9425G6KH. The challenge of this project is to have a synthesizable controller with zero timing errors at DDR 100MHz for 8-word burst writes and reads. Read the [ログインしてURLを表示] file in the archive [ログインしてURLを表示] for all...
FPGA implementation of Fractional Order function using VHDL, by using descrete function and any approximation methods.
Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.
This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.
Implementation of PID controller based FPGA using VHDL.
I have developed an OFDM waveform in MATLAB and have used the waveform developed to transmit image and text signals separately using USRP and captured the signals over-the-air with an SDR in the Lab. There are two tasks to be done. 1) To decode the captured signals with my code. 2) To modify the code to be able to automatically decode such over-the-air captured signals
partial reconfiguration of FPGA, FPGA hardware is needed, three analog sensors needed to integrate, these sensors are programmed partially so that , it can switch the usage without disturbing the rest part from working. I need someone who have work experience in partial reconfiguration. you can message me if you have any questions.