Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designersを採用する

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    15 仕事が見つかりました。次の価格: USD

    I have an FPGA in my application which generates digital signal and drives an external DAC for analog domain. However, the generated digital data has a lot of harmonic content which needs to be filtered out. In analog domain I calculated that a 7th order BW filter works well, cut off at 20kHz, > 60dB at 200kHz) I ask for a simulink model (open source, not encrypted) and document which describes...

    $172 (Avg Bid)
    $172 平均入札額
    15 入札
    Larger SD card 6 日 left
    認証完了

    Modify Atmel AVR program to accept both FAT and FAT32 SD cards. Present program will only recognize FAT up to 2 Gb.

    $96 (Avg Bid)
    $96 平均入札額
    6 入札

    This Project is to code exercises on latches, flip-flops and registers along with switches, lights and multiplexers VHDL -- Quartus Prime Lite 18.1 Quartus. Altera De-Soc board hardware implementation

    $32 (Avg Bid)
    $32 平均入札額
    3 入札

    I wanted to have one or two fpga bitstreams created for mining it depends on the board i have and how it's build i could give the model fpga i am going to use if that helps you better decide what to do to make the bitstreams compatible with the particular board or boards i will have.

    $39 / hr (Avg Bid)
    $39 / hr 平均入札額
    14 入札

    Looking to use the services of a developer with Serial Peripheral Interface protocol to have a Particle board talk with an eInk display.

    $1090 (Avg Bid)
    $1090 平均入札額
    29 入札
    AWR Design Environment software 5 日 left
    認証完了

    looking for someone having expertise in AWR Design Environment software. Determining the error vector magnitude in a communication transmitter as a function of the parameters of the power amplifier by establishing a simulator test bench to calculate the EVM for some basic modulation schemes and for simple amplifier models.

    $92 (Avg Bid)
    $92 平均入札額
    2 入札

    I need someone to do VHDL Lab for me. We have the code and we need to add some more functionality to it where it required in the exercise. Code is in folder ex1srcpy and ex1srcvhdl. You have explanation of what you need to do in the picture.

    $148 (Avg Bid)
    $148 平均入札額
    12 入札

    i wanna implement 128x128 and 1024 x1024 vector matrix Multiplication synthesizable code including xdc file for Artix edge 7 FPGA board it will support VIvado 2018.1 above

    $36 (Avg Bid)
    $36 平均入札額
    8 入札
    Verilog/VHDL task 4 日 left
    認証完了

    Hello freelancers. I have some works related to Verilog/VHDL and i am looking for someone who can work with me for a long term. I need someone who can handle simple as well as complex tasks. I will share details of work with selected freelancer.

    $21 (Avg Bid)
    $21 平均入札額
    20 入札
    Looking for FPGA expert 4 日 left
    認証完了

    I am looking for someone having expertise in FPGA, i am looking for someone for long term work relation. People having good experience in FPGA but new to this platform are most welcomed. i will explain the details of task in chat

    $37 (Avg Bid)
    $37 平均入札額
    15 入札
    JavaFX UI development 3 日 left
    認証完了

    6 Stop Round Table (Rotating at 60 degrees) SERVO 1 is connected to rotary table. Rotary table will rotate and stop at 60 degrees. Once it stops A, B,C, D, E & F as given below will be actioned. (A) Filling Quantity User can select the pre-set quantity shown in screen (B) ALIGNMENT: (Sensor, Stepper Motor) • Sensor to detect colour code. • Stepper motor will rotate and stop when c...

    $340 (Avg Bid)
    $340 平均入札額
    10 入札
    Xilinx developer in need_8263 -- 5 3 日 left
    認証完了

    A reliability enhanced video storage architecture in hybrid SLC/MLC NAND flash memory

    $146 (Avg Bid)
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    3 入札

    Re programming plc in ladder Short contract or freelance PLC & SCADA

    $36 / hr (Avg Bid)
    $36 / hr 平均入札額
    67 入札

    6 Stop Round Table (Rotating at 60 degrees) SERVO 1 is connected to rotary table. Rotary table will rotate and stop at 60 degrees. Once it stops A, B,C, D, E & F as given below will be actioned. (A) Filling Quantity User can select the pre-set quantity shown in screen (B) ALIGNMENT: (Sensor, Stepper Motor) • Sensor to detect colour code. • Stepper motor will rotate and stop when c...

    $307 (Avg Bid)
    $307 平均入札額
    9 入札
    PWM vhdl fpga 11 時間 left

    Description is in attached file. Note: Text is in Bosnian language so you will need to translate it.

    $156 (Avg Bid)
    $156 平均入札額
    11 入札