Verilog/ VHDL 仕事とコンテスト
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
Freelancerで仕事を検索
| プロジェクト / コンテスト | 詳細 | 入札 / エントリー | スキル | 開始日 | 終了日 | 価格(JPY) | |
|---|---|---|---|---|---|---|---|
| VHDL Radio Clock + python script | Need help in VHDL everything is mentioned on the PDF | 6 | エレクトロニクス, Verilog/ VHDL, ソフトウェアテスト, 電気工学, FPGA | Oct 19, 2017 | 本日6日 5時間 | ¥8063 | |
| Project for Gabriel G. | I need help with capsim practice rounds | 4 | プロジェクト管理, テレマーケティング, エクセル, Matlab and Mathematica, Verilog/ VHDL | Oct 18, 2017 | Oct 18, 20175日 18時間 | ¥2829 | |
| verilog project | making verilog on quartus II (cyclone IV) | 11 | エンジニアリング, Verilog/ VHDL, ソフトウェアアーキテクチャ, Assembly, FPGA | Oct 18, 2017 | Oct 18, 20175日 12時間 | ¥16633 | |
| Cloudsim project | I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. | 2 | C プログラミング, Java, Verilog/ VHDL, ソフトウェアアーキテクチャ, C++プログラミング | Oct 18, 2017 | Oct 18, 20175日 2時間 | ¥6922 | |
| Verilog programming - 18/10/2017 00:34 EDT | Simple verilog programming project. Create an ALU with full [URLが削除済みです、ログインして表示してください] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 11 | Verilog/ VHDL | Oct 18, 2017 | Oct 18, 20175日 | ¥11202 | |
| Verification Of Motion Estimator Using UVM | Verification Of Motion Estimator Using UVM(Universal Verification Methodology) | 5 | Verilog/ VHDL, 電気工学, Very-large-scale integration (VLSI) | Oct 17, 2017 | Oct 17, 20174日 23時間 | ¥26929 | |
| Verilog programming | Simple verilog programming project. Create an ALU with full [URLが削除済みです、ログインして表示してください] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 5 | Verilog/ VHDL | Oct 17, 2017 | Oct 17, 20174日 20時間 | ¥10070 | |
| ASIC Design in Verilog | This project is related to Computational Neural Networks | 2 | Matlab and Mathematica, Verilog/ VHDL, Neural Networks | Oct 17, 2017 | Oct 17, 20174日 16時間 | ¥9957 | |
| VHDL Radio clock | everything is going to be explained on the pdf | 11 | エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, FPGA | Oct 17, 2017 | Oct 17, 20174日 15時間 | ¥4470 | |
| Design of audio visualiser using DE2-115 Altera board | I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. | 4 | Verilog/ VHDL | Oct 17, 2017 | Oct 17, 20174日 13時間 | ¥26456 | |
| Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 13 | エンジニアリング, エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学 | Oct 17, 2017 | Oct 17, 20174日 7時間 | ¥15258 | |
| Matlab power system Simulation using Simulink | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 10 | エンジニアリング, エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学 | Oct 17, 2017 | Oct 17, 20174日 5時間 | ¥17801 | |
| エレクトロニクス, Verilog/ VHDL, マイクロコントローラ, 電気工学, LabVIEW | Oct 16, 2017 | Oct 16, 20174日 | |||||
| netlist construction in EE using C++ | refactor the sample code by using the c++ | 9 | C プログラミング, Verilog/ VHDL, C＃プログラミング, 電気工学, C++プログラミング | Oct 16, 2017 | Oct 16, 20173日 12時間 | ¥15275 | |
| project for Ahmed M -- 2 - 16/10/2017 12:09 EDT | I believe you must do this project. | 2 | Verilog/ VHDL | Oct 16, 2017 | Oct 16, 20173日 12時間 | ¥14370 | |
| project for Ahmed M | I believe you must do this project. | 1 | Verilog/ VHDL | Oct 16, 2017 | Oct 16, 20173日 12時間 | ¥17538 | |
| verilog project | want verilog code on fpga i want soon | 2 | エンジニアリング, Verilog/ VHDL, ソフトウェアアーキテクチャ, LabVIEW, FPGA | Oct 16, 2017 | Oct 16, 20173日 11時間 | ¥905 | |
| ASIC Designs and Development | Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... | 6 | エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, PCBレイアウト | Oct 16, 2017 | Oct 16, 20173日 5時間 | ¥1697 | |
| veriloghdl code for calculation area | THis must implement on quartus( altera FPGA cyclone IV) | 4 | C プログラミング, Verilog/ VHDL, マイクロコントローラ, C++プログラミング, FPGA | Oct 16, 2017 | Oct 16, 20173日 4時間 | ¥11654 | |
| making verlog hdl code | calculataion area in black and white image on fpga ( cyclone IV) | 8 | C プログラミング, Verilog/ VHDL, マイクロコントローラ, 電気工学, C++プログラミング | Oct 16, 2017 | Oct 16, 20173日 1時間 | ¥14143 | |
| VHDL Coursework | help in VHDL codes ,, everything will be explained later | 13 | エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学 | Oct 15, 2017 | Oct 15, 20172日 16時間 | ¥6255 | |
| fpga software | I want to read programmes in FPGA chips | 17 | C プログラミング, Verilog/ VHDL, ソフトウェアアーキテクチャ, FPGA | Oct 15, 2017 | Oct 15, 20172日 10時間 | ¥46730 | |
| creation of hardware module using verilog which will be able to communicate with the memory of the processor | using Verilog which will be able to communicate with the memory of the processor | 4 | Verilog/ VHDL | Oct 14, 2017 | Oct 14, 20171日 10時間 | ¥7015 | |
| simple verilog hdl code | calculate each area in black and white image | 11 | C プログラミング, エンジニアリング, Verilog/ VHDL, マイクロコントローラ, FPGA | Oct 13, 2017 | Oct 13, 201723時間 9分 | ¥5318 | |
| Simple Verilog Project | Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. | 8 | エンジニアリング, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA | Oct 13, 2017 | Oct 13, 201716時間 | ¥2716 | |
| Color space conversions and FPGA's | 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. | 9 | エンジニアリング, Verilog/ VHDL, 電気工学, FPGA | Oct 13, 2017 | Oct 13, 20176時間 1分 | ¥7468 | |
| Build software | Looking for expert in FPGA and verilog | 18 | C プログラミング, Verilog/ VHDL, ソフトウェアアーキテクチャ, C++プログラミング, FPGA | Oct 12, 2017 | Oct 12, 2017終了 | ¥54311 | |
| Statcom in simulink Power electronics expert -- 2 | Statcom in simulink Power electronics expert needed | 9 | エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, 電気工学, FPGA | Oct 11, 2017 | Oct 11, 2017終了 | ¥18576 | |
| Want to develop robotic program and test the same with simulation to check feasibility of and automation idea | Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... | 5 | Matlab and Mathematica, Verilog/ VHDL, ソフトウェアアーキテクチャ, ソフトウェア開発, Programming | Oct 11, 2017 | Oct 11, 2017終了 | ¥529500 | |
| VLSI PROJECTS | FIND THE ATTACHED IEEE [URLが削除済みです、ログインして表示してください] REQUIREMENTS | 4 | Verilog/ VHDL, FPGA, Very-large-scale integration (VLSI) | Oct 11, 2017 | Oct 11, 2017終了 | ¥9708 | |
| Statcom in simulink Power electronics expert | Statcom in simulink Power electronics expert needed | 9 | エレクトロニクス, Matlab and Mathematica, Verilog/ VHDL, FPGA | Oct 11, 2017 | Oct 11, 2017終了 | ¥12867 | |
| Convert a code from Aptech Gauss language into Matlab with Parallel processing. | I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. | 3 | Matlab and Mathematica, Verilog/ VHDL, ソフトウェアアーキテクチャ, CUDA, ソフトウェア開発 | Oct 10, 2017 | Oct 10, 2017終了 | ¥17289 | |
| Develop, Test and Implement it in software environment and simulate the circuit functionality - open to bidding | We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print. | 7 | エレクトロニクス, Verilog/ VHDL, 電気工学, デジタルデザイン, 回路設計 | Oct 10, 2017 | Oct 10, 2017終了 | ¥12062 | |
| Prelab | Write VHDL code | 7 | Verilog/ VHDL | Oct 10, 2017 | Oct 10, 2017終了 | ¥3055 | |
| dimensionality reduction using PCA | we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... | 14 | Matlab and Mathematica, Verilog/ VHDL, 有限要素解析（FEA）, CUDA, FPGA | Oct 10, 2017 | Oct 10, 2017終了 | ¥46164 | |
| ZYNQ c/ verilog project(s) | There is a Zynq C/ Verilog project involving BRAM and data structures , to be done. We will start with a 50 usd small project, on successful completion we will move into larger budget projects( a few hundred USD ones) .PM me to talk the details. | 11 | C プログラミング, Verilog/ VHDL | Oct 10, 2017 | Oct 10, 2017終了 | ¥9278 | |
| Altera DE115 - Audio signal processing | Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers | 9 | Verilog/ VHDL, マイクロコントローラ, 組み込みソフト, Assembly, FPGA | Oct 10, 2017 | Oct 10, 2017終了 | ¥25542 | |
| Audio Signal Processing | AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... | 7 | Verilog/ VHDL, マイクロコントローラ, 電気工学, 組み込みソフト, FPGA | Oct 10, 2017 | Oct 10, 2017終了 | ¥57549 | |
| Sequence Diagram | There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [URLが削除済みです、ログインして表示してください]() b. Call [URLが削除済みです、ログインして表示してください](Account) c. Call [URLが削除済みです、ログインして表示してください]() d. [URLが削除済みです、ログインして表示してください]() calls [URLが削除済みです、ログインして表示してください](amount) which makes the payment e. Call [... | 6 | Verilog/ VHDL, ソフトウェアアーキテクチャ, PLCとSCADA, 有限要素解析（FEA）, 製品図面 | Oct 10, 2017 | Oct 10, 2017終了 | ¥4186 | |
| Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) | Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [URLが削除済みです、ログインして表示してください] | 22 | エクセル, Matlab and Mathematica, Verilog/ VHDL, ソフトウェアアーキテクチャ, ソフトウェア開発 | Oct 7, 2017 | Oct 7, 2017終了 | ¥2457 | |
| UML/MARTE modeling | I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). | 1 | Verilog/ VHDL, UMLデザイン, 有限要素解析（FEA）, SAS, CATIAの専門家 | Oct 7, 2017 | Oct 7, 2017終了 | ¥66378 | |
| matlab report making 10 pages minimum | hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote | 10 | Matlab and Mathematica, Verilog/ VHDL, LaTeX, 数学, 物理 | Oct 7, 2017 | Oct 7, 2017終了 | ¥5431 | |
| Matlab Write a Function for Forward Kinematics of the RPR Robot | Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... | 16 | Matlab and Mathematica, Verilog/ VHDL, ソフトウェアアーキテクチャ, 有限要素解析（FEA）, ソフトウェア開発 | Oct 7, 2017 | Oct 7, 2017終了 | ¥4292 | |
| String compare algorithm | need an algorithm that would compare two long strings delimited by | | 3 | Matlab and Mathematica, Verilog/ VHDL, アルゴリズム, CUDA, 機械学習 | Oct 7, 2017 | Oct 7, 2017終了 | ¥221770 | |
| Cryptoanalysis - Cryptograpgy - C programming | I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. | 9 | C プログラミング, Verilog/ VHDL, ソフトウェアアーキテクチャ, プロローグ, C++プログラミング | Oct 6, 2017 | Oct 6, 2017終了 | ¥7794 | |
| MSF and DCF receiver | everything will me explained later | 5 | エンジニアリング, エレクトロニクス, Verilog/ VHDL, 電気工学, バイナリの解析 | Oct 6, 2017 | Oct 6, 2017終了 | ¥5174 | |
| Embedded Control System Design | It is a project on Embedded Control System Design. I will give the details later. | 12 | C プログラミング, Verilog/ VHDL | Oct 6, 2017 | Oct 6, 2017終了 | ¥4979 | |
| ABAQUS Model (CFRP Beam) | I need to make the results of this ABAQUS model converge with the experimental data curve (shown in the Excel sheet: Load vs Deflection). The current results shows a much higher yield and peak loading compared to the experimental data. The model files are attached to this project. | 13 | Verilog/ VHDL, 有限要素解析（FEA）, コンピューターグラフィックス, インダストリアルエンジニアリング, CATIAの専門家 | Oct 5, 2017 | Oct 5, 2017終了 | ¥21380 | |
| Simulation profile | need a private tutor for ANSYS-Fluent and ICEM-CFD | 8 | Matlab and Mathematica, Verilog/ VHDL, 有限要素解析（FEA）, FPGA, CATIAの専門家 | Oct 5, 2017 | Oct 5, 2017終了 | ¥18238 | |
| VHDL circuits project | have few questions on digital circuits that I need help with. will provide more details of interested | 23 | Verilog/ VHDL, 回路設計, Programming | Oct 4, 2017 | Oct 4, 2017終了 | ¥8688 |
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