Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designersを採用する

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    16 仕事が見つかりました。次の価格: USD

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    $107 (Avg Bid)
    $107 平均入札額
    5 入札

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    $142 (Avg Bid)
    $142 平均入札額
    5 入札

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comp...

    $70 - $140
    $70 - $140
    0 入札

    Design a circuit in Logisim for the following simple coffee vending machine: It accepts only coins of the nominal 10 coin and 50 coin . There are two types of coffee, costing: 120 coin and 170 coin. You can order a coffee only when there is enough money (use LED to indicate that you can order one or another type). Once you order, all the money is used without returning back any.

    $41 (Avg Bid)
    $41 平均入札額
    3 入札
    Digital circuit in logisim b 6 日 left
    認証完了

    Build a calculator that can add and subtract decimals of up to 5 decimal digits. The calculator should have a display of 6 decimal digits. There should a number pad with digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and three possible operations, + (addition), - (subtraction), = (equals). The flow of the operations should be as follow: While typing the number it should be displayed right aligned, extendin...

    $21 (Avg Bid)
    $21 平均入札額
    5 入札

    Design a circuit in Logisim for the following simple vending coffee machine: It accepts only coins of the nominal 10 coin and 50 coin . There are two types of coffee, costing: 120 coin and 50 coin. You can order a coffee only when there is enough money (use LED to indicate that you can order one or another type). Once you order, all the money is used without returning any.

    $30 (Avg Bid)
    $30 平均入札額
    7 入札

    MRAS SYSTEM SIMULATION USING SIMULINK NEEDED You will have 7 days to complete the work defined in scope. Your bid will not be negotiated so please read well before you bid. Payment will be 50/50 after simulation and after writting. Maximum Budget is 250USD

    $380 (Avg Bid)
    $380 平均入札額
    7 入札
    $430 平均入札額
    4 入札

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    $17 (Avg Bid)
    $17 平均入札額
    2 入札

    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

    $26 (Avg Bid)
    $26 平均入札額
    5 入札

    The project has a few basic functions. 1. maintain a specific temperature 2. fire a signal to a solenoid valve in particular (adjustable) intervals. other basic functions like on off etc

    $186 (Avg Bid)
    $186 平均入札額
    40 入札

    Verilog simulation of two action-reaction processes

    $29 (Avg Bid)
    $29 平均入札額
    6 入札

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    $214 (Avg Bid)
    $214 平均入札額
    7 入札

    Vhdl is needed

    $27 (Avg Bid)
    $27 平均入札額
    6 入札

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    $508 (Avg Bid)
    $508 平均入札額
    14 入札