Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Verilog / VHDL Designersを採用する

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    15 仕事が見つかりました。次の価格: USD

    I want help in learning physical design

    $37 / hr (Avg Bid)
    $37 / hr 平均入札額
    2 入札

    I need you to design a basic processor that performs the basic operations (addition, subtraction, division, multiplication) with the software "Proteus 8.8".

    $20 (Avg Bid)
    $20 平均入札額
    2 入札

    Requiero que me realizen el diseño de un procesador basico que realize las operaciones aritmeticas basicas (suma,resta,division,multiplicacion) con el software de "Proteus 8.8".

    $30 (Avg Bid)
    $30 平均入札額
    1 入札

    diseño procesador básico de 8 bits con unidad de control rígida cableada, simulación en programa proteus

    $33 (Avg Bid)
    $33 平均入札額
    3 入札

    I want to implement on NetFPGA SUME board. I post my pre report below.

    $182 (Avg Bid)
    $182 平均入札額
    2 入札
    Trophy icon FPGA DDR controller (Verilog) 19 日 left

    The objective of this project is to write a Verilog 100MHz SDRAM DDR controller. The controller shall run on a Lattice LCMXO3L-4300E-6MG121I connected to a Winbond 256MBit 16-bit W9425G6KH. The challenge of this project is to have a synthesizable controller with zero timing errors at DDR 100MHz for 8-word burst writes and reads. Read the [ログインしてURLを表示] file in the archive [ログインしてURLを表示] for all...

    $250 (Avg Bid)

    FPGA implementation of Fractional Order function using VHDL, by using descrete function and any approximation methods.

    $373 (Avg Bid)
    $373 平均入札額
    9 入札

    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

    $121 (Avg Bid)
    $121 平均入札額
    9 入札

    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

    $154 (Avg Bid)
    $154 平均入札額
    3 入札

    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

    $179 (Avg Bid)
    $179 平均入札額
    1 入札

    Implementation of PID controller based FPGA using VHDL.

    $107 (Avg Bid)
    $107 平均入札額
    18 入札

    I have developed an OFDM waveform in MATLAB and have used the waveform developed to transmit image and text signals separately using USRP and captured the signals over-the-air with an SDR in the Lab. There are two tasks to be done. 1) To decode the captured signals with my code. 2) To modify the code to be able to automatically decode such over-the-air captured signals

    $259 (Avg Bid)
    $259 平均入札額
    5 入札
    Need FPGA RTL engineer 1 日 left
    認証完了

    Kindly share your availability and rates for a image processing module to be developed in FPGA.

    $19 / hr (Avg Bid)
    $19 / hr 平均入札額
    11 入札

    partial reconfiguration of FPGA, FPGA hardware is needed, three analog sensors needed to integrate, these sensors are programmed partially so that , it can switch the usage without disturbing the rest part from working. I need someone who have work experience in partial reconfiguration. you can message me if you have any questions.

    $115 (Avg Bid)
    $115 平均入札額
    3 入札

    I want to implement a paper using verilog coding.. Kindly review paper before biding

    $25 (Avg Bid)
    $25 平均入札額
    5 入札