Design of a pipelined based multiplier accumulator unit for Image processing purpose

With +5 years of experience in digital design using Verilog HDL language. Starting from designing small architectures from microprocessor tell implementing the wifi 802.11a standard on FPGA. I'm working now on the implementation of FFT using CORDIC Algorithm you can check my publication here : [login to view URL] I'll be glad to help you. Note: I've solved the problem and the project is running well now :)

I am working as FPGA design engineer since last 6 years. I have worked in image preocessing domain for 5 years. I have expertise in both verilog and vhdl. I can complete this job with greater accuracy.

Hi, we have many years experience working with Xilinx/Altera FPGA and Verilog/VHDL programing languages. We can surely help you solve the problem. Could you please share more details about your issue? What is your problem: Compilation error or synthesis error or wrong result when running simulation or wrong result when running on real FPGA? How are you sure that the problem come from MAC unit design? More information is preferable so that we can help you in detail. Thanks,