Serial Peripheral Interface is basically used to allow the Microcontroller unit to communicate with many peripheral devices. The serial clock synchronises the shifting data serially through two serial lines. Master controls the interchange by controlling the clock line. SPI is a synchronous serial data bus. This report describes the design of Serial Peripheral Interface using VHDL and simulate using simulator. The transmitting and receiving parts are designed by taking the logic from the Parallel–in Serial–out shift register and Serial –in Parallel–out shift register. SPI interface is designed and then it is interfaced with Microcontroller bus interface. The microcontroller bus interface is designed to read, write and data transfer with the registers .Basica...
Please help me to implement the MPIS single cycle CPU
Skills required: * Experience with Xilinx Virtex-5 or Virtex-6 FPGA * Experience with Xilinx EDK designs * Competent in VHDL Extras: * Experience with XUPV5 development board * Access to a XUPV5 development board The job is to develop a peripheral core in VHDL and a test project for EDK to verify the core on the XUPV5 board. The peripheral will use the PCI Express Endpoint internal core of the Virtex-5 FPGA and provide a user FIFO interface. The peripheral will contain a DMA scatter gather engine to enable the software in the host PC to setup DMA transfers between the host PC and the FIFOs. There will be 8 FIFOs (or channels) that can be targeted by the host software.
We are looking for a vhdl implementation on the spartan 3e board which must be utilizing the board's DAC feature. We also need additional two to three additional features/implementations on this same project from any of the following spartan 3e features: a) VGA port b) RS232 port c) PS/2 keyboard d) ADC e) SPI f) Ethernet g) Expansion connectors h) LCD screen Free reign of selection above and manner of implementation is given as long as it could be done very soon. 3 days or less may be preferred. Also, we request commenting each section of the code and an accurate overall explanation of the project. Hopefully, you could now be the right person for it!
...an open source part to convert from graphical representation to VHDL. If the end user buys my application they download a plugin for your application which allows them to error encode the design. If they do not buy my application they can still use the software for chip design. You would write the open source graphical program and build the website. It would be similar to Simulink from Mathworks but it would not include a simulation environment. To simulate a design you call the programs to generate VHDL, then call an open source VHDL simulator to do the simulation. It would then call an open source waveform viewer to look at the results of the simulation. Here is a list of simulators, only some of them handle VHDL:
Hi All, We have urgent need for someone who holds strong expertise in CCD/CMOS Camera Hardware Design as well as associated IP development in VHDL. Skills required ( Must ) : - Must have strong experience in CCD/CMOS Camera Hardware Development. Must have experience with different kinds of image sensor. - PCB Schematic, BOM, PCB Placement, Layout, Routing etc. - IP development for the given hardware in VHDL we are looking for someone who can work for us remotely on part-time or contract basis. we are looking for someone for long term relationship. we have couple of projects available, we will discuss the project details with the selected person. Please contact us for detail. I would really appreciate if only serious bidders react on this project work. Applic...
I need a program to continuously capture the data from the ADC on the Spartan 3A or Spartan 3E board and stream it out over the ethernet on the board. The 2 ADCs on the boards are 12/14 bits with a m...com/products/boards/s3e1600e/ ,plasma ONLY in VHDL, no Verilog, please do not ask. No upfront payment, payment guranteed with e-screw after receiving working simulation and code. PLEASE : if you ask for pre-pay, I decline your bid right away.
pls check the attachment for details i want u to do this work very fast i can pay 50$ pls use Altera software with small report of in ur own words but deadline is very strict pls help
...question 16, you need to write the verilog code and simulate it using Modelsim or any other circuit simulator to verify the code. You'll need to submit the complete code and the simulator results (waveform). These are undergraduate level stuff, so you should find them pretty easy, but If you need explanations or help, you can ask me ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). For question 16 in the attached file, you need to provide: 1) Verilo...
Write the VHDL description of the 32-bit MIPS ALU whose details are described above. You should simulate your design using ISE or another VHDL simulator to prove the correctness of your design. Prepare a short report with the VHDL codes and the simulation results. IT IS A VERY EASY JOB FOR WHO KNOWS VHDL. It's one of my lab project. Details of Job attached.
...each of them, you need to write the verilog code and simulate them using Modelsim or any other circuit simulator to verify the code. You'll need to submit the complete code and the simulator results (waveform). These are undergraduate level stuff, so you should find them pretty easy, but If you need explanations or help, you can ask me. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). For each of the two questions (13, 14), you need to provide: 1) Ve...
Zlecenie polega na uproszczeniu projektu demonstracyjnego w Quartusie 9.1. Należy usunąć zbędne elementy oraz okomentować kod. Proszę licytować koszt wykonania tych czynności, w komentarzu dodatkowo proszę podać cenę "konsultacji" za godzinę.
i want to design a softcore processor using SOPC builder too...real time video processing using FPGA. i want the code to be written in either VHDL or C. the design of softcore processor is similar to the tutiorial given in the altera website under name"introduction to SOPC builder using VHDL" ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). i want the project in running condition. i want to coder to run project on fpga. ## Platform i want to run project on ...
Development of a PID controller in HDL (VHLD or Verilog) for Xilinx FPGA Spartan 6. The development shall be with WEBPACK Xilinx. The? implemented PID shall not be larger than 400 slices. The The PID shall be developed? at 32bits precision, and intermendiate values extended at 48 bits and shall include: • command ??" The setpoint, as commanded. • feedback ??" as measured by a feedback device. • output ??" The elaborated output command that is the control signal . • error ??" is command minus feedback. • enable ??" A bit enabling the PID. If false, all integrators are reset, and the output is forced to zero. If true, the loop operates normally. The PID gains, limits, and other ’tunable’ features of the loo...
Project: Ethernet Hub/Repeater on FPGA Ethernet: 10/100 Base, Opencore IP Connection: 2 IP Core + Host Languages required: HDLs (Verilog, VHDL), HVLs (Tcl, Perl), C Required skills: Ethernet, FPGA design - If this work is successful, I have more project to work together. - Compensation is based on your contribution. We will work together, and I can handle all. But, I may expect at least around 50% contribution, sorry not for entry level. - Local (Toronto Canada) preferred, but not mandatory.
This project is in Verilog and is 80% complete for a simple pipelined cpu. The are steps to be followed in the zip file to get the final correct wave form. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). ## Platform Windows XP, ModelSim, Verilog
This project is in Verilog and is 80% complete for a simple multi cycle cpu. The code in comments needs to be uncommented and correct signals coded to complete the design. Further details are in the zip file.
hi .i hav to convert a 4bit audio signal and convert it to A-to-D by spartern 3e, after that the digital signal has to be converter to D-to-A , I want to know is it possible to do by spartern 3e?? if yes then how...plz help me its my m-tech project....plz send the sollution by .
Need to design a FPGA Temperature monitoring system using VHDL. The target board used is a Spartan 3A starters development kit. Temperature sensor is a K-type thermocouple connected via the RS232 port. Refer Sensor circuit attached. Readings should be displayed in the onboard LCD of the target board.
...I'm not very familiar with Verilog, so the implemention is messy. I want someone to look at my Verilog code and show me how it should have been written, making the I2C decoder it's own module, being able to write data to several registers. The code should compile on the free Altera Quartus II programming environment, but doesn't need to be tested on an actual CPLD. ## Deliverables 1) All deliverables will be considered "work made for hire" under U.S. Copyright law. Employer will receive exclusive and complete copyrights to all work purchased. (No 3rd party components unless all copyright ramifications are explained AND AGREED TO by the employer on the site per the worker's Worker Legal Agreement). ## Platform Using the free Quartus II...
Hi Sir, My project is to design a Barrel processor (architecture design and coding in VHDL). I have no prior experience in this field. Can you help me out. I have given a short note on my project below. I have to design a barrel processor that has to execute only one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the Barrel processor and has to implement the processor on a FPGA by using VHDL. So, I have to take a basic architecture of any of the processor and have to modify it such that the processor has N - number of PC,SP,SR,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time...
I need simple solution for analog-to-digital conversion using the Xilinx Spartan 3E FPGA and the onboard A/D converter on Xilinx Spartan 3E Starter Kit development board. I need to sample signals on 2 channels of the A/D converter with the sampling frequency of about 1.5 MHz. The solution should be developed as an vhdl-module.
I need an Electronics Engineer with good experience in VHDL programming, PCI board design, DMA. The deliverables are schematics, gerbers, and BOM.
A rather simple SystemC project (cosisting of 14 cpp files of the size similar to the one accessible at ) is to be converted into synthesizable VHDL (ISE 10.1 project). The conversion can be done manually or automatically (using an adequate EDA tool), the only requirement is that the code has to comile and synthesize on the ISE. I can pay for the task up to 125 USD.
Filter FIR in VHDL for cut low , med and high frequencies of audio.
Assignement is due on thursday afternoon 5.00 pm australian time and its long and has to be done using XILINX and verilog
Ok, I'm in need of someone who can make a well documented (comment in code) VHDL file. I'm trying to make a buzzer circut in VHDL. (The image of the circut is attached). Basically the buzzer would go off if someone turned on the ignition and either the car door was opened and/or the seatbelt wasn't on. It would be good if I can have this done by tomorrow night at the latest.
VHDL project Includes coding, initial report and final report. The board being used is: Altera® DE1 Development and Education board
See attachment. Would need completed by 5/3/10. Thank you. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Worker in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will...
design a simulator for a dynamically scheduled CPU using scoreboard algorithm and the tomasulo's algorithm for the scoreboard assuming a MIPS like basic arithmetic instructions (+, -, *, /). add and subtract have latencies of 2 cycles, multiply has a latency of 10 and divide has a latency of 40 be done using any high level language or HDL's like C, C++, verilog etc ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed
Very simple VHDL program, It involves creating a design that can be tested and bench. The requirements are in the file.
The particular problem allocated to you is selected by taking modulus(school ID, 2) + 1; for example modulus(0572796, 2)+1=0+1=problem 1. For each problem, use Sonata VHDL software to design the system and the corresponding test bench in accord with the stated functionalities.
This is a small project. Please read attached documenation
The particular problem allocated to you is selected by taking modulus(school ID, 2) + 1; for example modulus(0572796, 2)+1=0+1=problem 1. For each problem, use Sonata VHDL software to design the system and the corresponding test bench in accord with the stated functionalities.
