hi,
i have done 3 bigger projects and more than 25 projects on Verilog ,VHDL , SysemVerilog, UVM
i will explain all things in 2 week,
after that you will be able to work on any one of this language,
i have more than 10 assignment for all languages ,we will do one assignment in each session.
thanks & regard
kundan vaghela
+91 9173500753