終了

signal generator

Target: ATtiny11-6PC or -6SC Inputs: 1. Enable. TTL, active low. Outputs: 1. Out1. TTL, active high. 2. Out2. TTL, active low (inverse of Out1). Circuit details: Run on internal clock if possible. Supply voltage is 5V. Functional details: Define constants t0, t1, t2, all byte values with ranges: t0 [0..1] seconds t1,t2 [0..1] milliseconds Implement a state machine with states [inactive, energize, pulse]. Upon reset, enter state "inactive". Upon assertion of Enable, enter state "energize" and begin timer of t0. Remain in state "energize" while Enable remains asserted and until timer expires then enter state "pulse". Remain in state "pulse" until Enable is deasserted. While in this state, assert output for time t1, then deassert output for time t2, repeat. In any state, if Enable is deasserted, enter state "inactive". State Out1 Out2 inactive 0 1 energize 1 0 pulse pulse pulse

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):

a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.

b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.

3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).

* * *This broadcast message was sent to all bidders on Thursday Sep 29, 2005 3:33:32 PM:

I have added a timing diagram of the "signal generator" to help describe the function of the design.

* * *This broadcast message was sent to all bidders on Saturday Oct 8, 2005 1:08:21 PM:

I have updated the ZIP file to include the schematic instead of just the timing diagram.

## Platform

Target: ATtiny11-6PC or -6SC Inputs: 1. Enable. TTL, active low. Outputs: 1. Out1. TTL, active high. 2. Out2. TTL, active low (inverse of Out1). Circuit details: Run on internal clock if possible. Supply voltage is 5V.

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さらに表示: web design generator, web circuit design, hire generator, generator hire, design generator, signal, byte time, state machine, voltage design, state diagram, circuit design program, voltage supply, signal generator circuit, ttl design, circuit generator, engineering inputs, pulse generator, software schematic diagram, clock seconds milliseconds, clock seconds

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