I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board.
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The code works fine and I can see the blinking LED. However, if I un-comment line 59 in [login to view URL], the chip programming would fail at 85% (attached image).
How to fix the issue?