Design an 8-bit Multi-Match Prioritizer using HDL description
$10-30 USD
処理中
投稿日: 6年以上前
$10-30 USD
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The conventional (single-match) priority encoder finds only one match, i.e. the highest priority input. An n-bit MPZ unit finds r (1 ≤r≤n) matches in exactly r cycles. Design an 8-bit MPZ using HDL description. You may use ModelSim or Quartus II software. In your implementation, you may have a mix of behavioral and structural descriptions for modules/components. Slight modifications of the unit, compared to those provided in Section III are allowed. Your report for this problem should include the HDL code of your MPZ design and simulation results to show the correct behavior, or any other interesting observation (e.g. maximum clock frequency of the design).