alarm clock

Design the control logic for an alarm clock (for simulation purposes 20ns simulation = 1 minute real time – this can be adjusted somewhat for simulation purposes).

a) Use multiple input signals (alarm set input, the snooze, and the alarm time).

b) The design will contain one output (Alarm_On). A logic high at the output represents the alarm being “on”.

c) An input will be used to set the alarm off.

d) When the simulation starts, a counting mechanism will start counting (representing/roughly simulating a clock).

e) If the alarm set input signal is high, then the alarm should turn on when the count equals the preset alarm value. If at any point during the simulation the alarm set input is switched off, the alarm should turn off by the next complete clock cycle.

f) If the snooze button is activated (assume that snooze is a pulse that is at least one full clock cycle in duration) the alarm should turn off and then turn back on after 5 minutes.

g) Repeat snooze button simulations (pulses) should cause the same behavior in the circuit.

h) If at any time the alarm set input signal goes low, the Alarm_On output should go low by the end of the next complete clock cycle.

i) Clearly describe any additional rules or assumptions.

Write a VHDL or Verilog code that implements the above alarm clock. Use one-hot encoding for state encoding. Verify the functionality and behavior of the circuit. Use Quartus II toolset. Submit a report containing the following:

1. A state diagram showing the implementation of your design (overview of your design, a detailed description of your approach and design process). Clearly show all the states and the conditions on which transitions occur.

2. Hardcopy of your code.

3. Hardcopy of annotated (properly labeled) waveforms that demonstrate all the required behavior.

4. RTL schematic of the design after compilation.

5. Roughly, draw the implied hardware of your code. Provide a brief comparison between the tool's RTL schematic and the implied hardware you drew.

6. Extract the highest clock frequency of your design from the compilation report.

Verilog/ VHDL

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