A (PSK) modulator/ demodulator for the ZYNQ platform is needed.

$250-750 USD

クローズ

投稿日:

約7年前

$250-750 USD

完了時にお支払い

A (PSK) modulator/ demodulator for the ZYNQ platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK,8-PSK) modulator/ demodulator for the ZYNQ (ZC706) platform is needed. The developer will add the PSK (BPSK, QPSK,8-PSK) modulator/ demodulator core into the ADRV9371 HDL Reference Design.([login to view URL]) The PSK modulator will be placed in the Transmit Path (possibly at the DAC UNPACK stage) The PSK demodulator will be placed in the Receive Path (possibly at the ADC PACK stage) The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selection between 1ksps-200 MSPS,(100 MSPS for BPSK) The Input to the modulator should be selectable (a PRBS sequence or Stream from a TCP/IP port) The output of the demodulator should be a Stream to a TCP/IP port. (In case of a PRBS sequence, the demodulator should indicate a LOCK) Control: The control parameters should be set through a TCP/IP port. User Interface: The bidder must provide basic SW that can control the parameters of the design, Send and receive data through TCP/IP ports. Test: As the TX/RX JESD IP's have to be purchased seperately we will test the design using our ADRV9371 test setup. The bidder should also initiate a loopback between the AD9371 IP's TX-RX path. The modulator/ demodulator should work at any selected bit rate. This project is a mere test for the abilities of the [login to view URL] are aware that this design can be realized by using Mathworks and Vivado HLS reference designs. If the bidder is sucessfull, we will ask for; A pulse shaping Filter,(TX,RX) A Viterbi decoder(an existing one), Sync Word Insertion, Detection, Reduced Rate FFT, BER count, SNR estimation blocks to be added by the bidder to the existing project for an extra fee.

プロジェクト ID: 13569668

プロジェクトについて

11個の提案

リモートプロジェクト

アクティブ 7年前

お金を稼ぎたいですか？

メールアドレス

Freelancerで入札する利点

予算と期間を設定してください

仕事で報酬を得る

提案をご説明ください

登録して仕事に入札するのは無料です

この仕事に11人のフリーランサーが、平均$619 USDで入札しています

@ahmedmohamed85

A proposal has not yet been provided

$722 USD 10日以内

5.0

(284 レビュー)

7.5

@ducdctoandh

Bid Summmary Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG.

$750 USD 10日以内

4.9

(53 レビュー)

5.5

@oharwot

Hello I have done similar task. The PSK modulator is easy. The demodualtor is hard. If you want synchronous demodulator and bitrate 200 MSPS it is challenge! The async demodulator is easy. The task is not problematic it is just lot of work. Do you have the board? I would like to do the desin in System Generator. Data stream over ETH is different task - you need quite high bitrate but it is possible. I have some experience and around 800 Mb/s is possible with Zynq. Regards Ondrej

$722 USD 100日以内

5.0

(6 レビュー)

2.7

@prashushinde9

I want to discuss this project with you further, let me know the best suitable time for you to schedule the meeting, Feel free to message me at any time, i used to be online 14 hrs in a day on this website so probably you will get a quick response from my end.

$773 USD 20日以内

0.0

(0 レビュー)

0.0

@muarslan

Dear rd13new, First of all, thank you very much for your invitation to bid for this exciting project, I sincerely appreciate. I had quite a hands-on experience on ZC706 during my career (exploited many features of Zynq SoC, both at Programmable Logic part and Processing System part). Relevant to your project, I had the chance to work with a similar RF chip during my employment at Aselsan before moving to UK. AD9361 RF chip was a strong candidate for the implementation of the RF subsystem in one of the projects we were assigned to. I had the chance to experiment on the integrated ZC706-AD9361 setup, taking the corresponding AD HDL reference design as a starting point. I would absolutely be interested to work on your project. I read the project description carefully (thanks very much for the very well defined description). What I can say in my first glance is that, one of the challenges seems to be the variable sampling rate selection. We can utilise the programmable User Clock (Silicon Labs - Si570 Oscillator) on ZC706 which can provide us with clock frequencies in the range of 10MHz-810MHz. Apart from this, or maybe together with this, internal FPGA clocking resources (MMCM) could also be candidate for clock generation with variable frequencies. The question of how much time we would tolerate when we are switching from one sample rate to the other would affect implementation, obviously. Actually, I had more things to say, but there's this character limit here. Thanks.

$777 USD 20日以内

0.0

(0 レビュー)

0.0

@appsmarket

Hello, Thanks for posting this project. Here we read your requirement and understand it. We have some queries . So we want to discuss with you. Please message us then we can discuss in detail and provide you exact estimate and start work. Thanks

$370 USD 10日以内