Dear rd13new,
First of all, thank you very much for your invitation to bid for this exciting project, I sincerely appreciate.
I had quite a hands-on experience on ZC706 during my career (exploited many features of Zynq SoC, both at Programmable Logic
part and Processing System part). Relevant to your project, I had the chance to work with a similar RF chip during my employment
at Aselsan before moving to UK. AD9361 RF chip was a strong candidate for the implementation of the RF subsystem in
one of the projects we were assigned to. I had the chance to experiment on the integrated ZC706-AD9361 setup, taking
the corresponding AD HDL reference design as a starting point.
I would absolutely be interested to work on your project. I read the project description carefully (thanks very much for
the very well defined description). What I can say in my first glance is that, one of the challenges seems to be
the variable sampling rate selection. We can utilise the programmable User Clock (Silicon Labs - Si570 Oscillator) on
ZC706 which can provide us with clock frequencies in the range of 10MHz-810MHz. Apart from this, or maybe together
with this, internal FPGA clocking resources (MMCM) could also be candidate for clock generation with variable frequencies.
The question of how much time we would tolerate when we are switching from one sample rate to the other would affect
implementation, obviously.
Actually, I had more things to say, but there's this character limit here. Thanks.