Dma controller design for amba ahb bus

終了済み 投稿 7年前 着払い
終了済み 着払い

The project has amba ahb bus it will have two masters dma and cpu dlave is sram, a fifo is connected to dma at first the source address in sram is invoked by cpu and the adress from sram is transferred to dma via bus and from dma to the fifo the output data comes from fifo simply speaking the data in source of sram is the output of fifo. The cpu is like heart of the project because it initializes the address in sram and invokes dma when the data comes to the dma.

Verilog/ VHDL

プロジェクトID: #10139172

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5個の提案 リモートプロジェクト アクティブ 7年前

5人のフリーランサーが、平均$216 で、この仕事に入札しています。

luffy08

Hello Sir, Please go through my profile and contact me for more information. I am looking forward to an opportunity to work with you. Thank you for your consideration luffy08

$150 USD 3日以内
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rohi1710rohi1710

I have worked as FPGA design engineer for 6 years and I have expertise in both verilog and VHDL. I have worked in DMA project and many other memory controllers in my career. I can complete this job with greater accurac もっと

$255 USD 7日以内
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