終了

Designing a testbench in verilog

この仕事に、25人のフリーランサーが、平均₹1272で入札しています。

ahmedmohamed85

A proposal has not yet been provided

₹1500 INR 1日以内
(283件のレビュー)
7.5
raulbehl

Hello! Please check my reviews to know a bit about me ! Thank you

₹1500 INR 1日以内
(47件のレビュー)
5.6
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS もっと

₹1500 INR 1日以内
(5件のレビュー)
4.6
SANGITAR

I am ready to take on the task,have proficiency with verilog. you can expect 100 percent time bound results, will complete asap.

₹2250 INR 1日以内
(3件のレビュー)
4.1
SqUa11

Hello, My name is Mohamed. I have 5 years experience in VHDL and VErilog. I checked your project description and I can handle ur task contact me for more details. Regards

₹1300 INR 1日以内
(15件のレビュー)
3.9
₹1500 INR 1日以内
(14件のレビュー)
4.2
₹1300 INR 2日以内
(12件のレビュー)
3.9
jasnaikaran

Hello, I am an electronics engineer having experience of FPGA based digital system design for more than 5 years.

₹850 INR 1日以内
(4件のレビュー)
3.1
pepsmich

Hi, I can help you get this done. I did at least 2 vhdl codes in this site and both had testbenches for simulation. I cannot see any attached file. Should you be interested, please let me know.

₹1300 INR 1日以内
(2件のレビュー)
2.4
luffy08

Hello sir, I am a professional hardware engineer. I've done many projects on IP core using Verilog. It would be my pleasure to work on your project. Please contact me to discuss the details. Thank you for your cons もっと

₹1500 INR 1日以内
(3件のレビュー)
2.5
abuzduga

Do you want support for assertions in your testbench ? SVA ? Do you have a timing diagram ? Is there a need for special software, like Quartus or Modelsim ?

₹1250 INR 2日以内
(1レビュー)
2.3
SepaliArawwawala

hi I am a university student who is following an Electronic Engineering degree and I think that i will be able to fulfill your desired job since I have done IELTS and I have a good proficiency in English as well and I もっと

₹1250 INR 2日以内
(3件のレビュー)
0.8
SEELaboratory

I have expearence in Altera Quartus and Modelsim. So, can write code in Quiartus and I can test it in Modelsim. I am ready to do it at a lower price for reviews.

₹600 INR 2日以内
(0件のレビュー)
1.4
dangluonghoangvu

Hi guys, I am an Logic design engineer. I think i can help you on this project. I have enviroment for simulation and i can release code and simulation result (picture file or wave file). Thanks, Vu

₹1250 INR 1日以内
(0件のレビュー)
0.0
maninder10061996

I am new to freelancing but have a handsome experience in verilog as i have done and tested several projects on my know in verilog. i hope the above line explains a low fee for this project. The inputs i will be requir もっと

₹601 INR 1日以内
(0件のレビュー)
0.0
Garima031

I want to try this in a minimum span.

₹900 INR 2日以内
(0件のレビュー)
0.0
manojexp86

A proposal has not yet been provided

₹1050 INR 1日以内
(0件のレビュー)
0.0
joshipriyankk

- test bench in verilog / system verilog . - possible test case list with standard test bench code. - verification environment architecture. - batch mode display for important signal.

₹1150 INR 1日以内
(0件のレビュー)
0.0
burhanmudassar

Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include: - PHY Layer Design on FPGA for Software Defined Radio P もっと

₹1250 INR 1日以内
(0件のレビュー)
0.0
vw1736128vw

Hello, I'm an experienced IC design engineer and I can help in achieving what is required. So please feel free to contact me in order to get more details on the requirements so that we can plan the work to do. Best もっと

₹1300 INR 1日以内
(0件のレビュー)
0.0