Design Serdes (Serializer De-seralizer) on Altera MAX10

Specification:

The serdes circuit should take 16 16-bit data from one memory and transfer it to another memory serially.

The design will have 2 parts.

Following should be the functionality:

Part 1

Data from a preset memory (16 locations of 8-bits each) is converted to a serial stream of data and sent out of the FPGA chip through a single pin...

Part 2

...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits).

The data in this memory should match with the data in memory in Part 1.

Both parts are to be implemented in the same FPGA ....The serial out from part 1 will be physically connected with a wire to the serial input in part 2 (in a loopback configuration)

This circuit should display the contents of memory in part 2 on seven segment displays.( two seven segment)

A pushbutton should be used to single step through all the memory locations...remember the contents displayed should match what was preset in the memory in part 1

Verilog/ VHDL

プロジェクトID: #12090353

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