Hi
I have seen your requirement and sounds very interesting to me and basically belongs to my skill set i.e. which is UVM and SystemVerilog , I have 10+ years of Design and Verification Experience and worked for top notch Chip and EDA Companies , Basically I understand of generating concept of UVM Testbench but are you expecting the Test-bench should be generic which can written for any IP ? or you want to right for specific IP only ? I would prefer to write product in perl , even I wrote personal template generator & code generator for my personal usage. it is possible to write basic read/write based auto generated test bench , it would be great if you send me your idea in blocks what exactly you want to generate from register description ? please provide some more details about work
Thanks
Shobhit K.