A synthesizable implementation of ECC engines

The implementation may be a mixed HW-SW approach. May include multiple implementations, codes or algorithms. Use data in block sizes of 512B, 1K, 2K, 4K ECC must be able to detect at least 42 bit errors per 1KB Memory input/output in 8, 16, 32 or 64 bits. Engine input/output left up to implementer Clock of at least 50MHz (if using 90nm library) The implementation may be a mixed HW-SW approach. ECC Encode and Decode done by HW but correction done by SW. More information will be provided to bidders.