Wanted technical writer for VLSI DFT

Closed

説明

Wanted technical writers who has knowledge in VLSI semiconductor DFT domain .

Main requirement is, given the lead, guidance and the basic outline of the concepts to be followed in book , the writer should be able to explore, formulate and ready the content on his own with practical examples, for my further review & correction, since for me time is a strict constraint .

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VLSI

Design For Testability

(DFT)

A Practical Approach

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CONTENTS

[url removed, login to view]

[url removed, login to view] and Quality

[url removed, login to view] for Testability

[url removed, login to view]

[url removed, login to view] Compression

[url removed, login to view]

[url removed, login to view] Simulation

[url removed, login to view] Built-In Self-Test

[url removed, login to view] Testing and Built-In Self-Test

10. JTAG

11. Core-Based Testing

12. Test mode timing closure

13. High Speed IO Testing

14. Analog DFT

15. Chip & Wafer level Testing

スキル: 回路設計, デジタルデザイン, エレクトロニクス

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プロジェクトID: #11774833