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    1,375 verilog projects 仕事が見つかりました。次の価格: USD

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $193 (Avg Bid)
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    7 入札

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $146 (Avg Bid)
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    2 入札

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $415 (Avg Bid)
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    2 入札
    DSP48E1 help 1 day left

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
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    5 入札

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    $18 (Avg Bid)
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    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $154 (Avg Bid)
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    7 入札

    Hello freelancers I have a lot of projects in all engineering fields so i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned

    $38 (Avg Bid)
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    verilog coding using putty or terminal. if you are interested i will give more information.

    $135 (Avg Bid)
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    27 入札

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    $104 (Avg Bid)
    $104 平均入札額
    9 入札

    mtech Verilog project

    $21 (Avg Bid)
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    19 入札

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
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    7 入札

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    $2830 (Avg Bid)
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    15 入札

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    $108 (Avg Bid)
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    12 入札

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    $101 (Avg Bid)
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    2 入札

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    $20 / hr (Avg Bid)
    $20 / hr 平均入札額
    9 入札

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    $131 (Avg Bid)
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    12 入札

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    $4436 (Avg Bid)
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    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $390 (Avg Bid)
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    3 入札

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    $65 (Avg Bid)
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    $21 / hr 平均入札額
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    $23 平均入札額
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    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $46 (Avg Bid)
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    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

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    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

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    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
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    20 入札

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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    We are looking for a System Verilog Training for few Engineers in our premises.

    $1988 (Avg Bid)
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    5 入札

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
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    8 入札

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $122 (Avg Bid)
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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
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    15 入札

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
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    5 入札

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
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    11 入札

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
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    7 入札

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    $128 (Avg Bid)
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    3 入札

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $72 (Avg Bid)
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    1 入札

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
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    1 入札

    I need image encryption using verilog on FPGA board

    $803 (Avg Bid)
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    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

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    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    $563 (Avg Bid)
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    $80 平均入札額
    1 入札

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    $45 (Avg Bid)
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    8 入札
    Quartus Ended

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    $27 (Avg Bid)
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    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    $106 (Avg Bid)
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    10 入札

    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

    $20 (Avg Bid)
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    i need a code for serial multiplier using verilog not from online please

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    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    $108 (Avg Bid)
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    Need help cleaning up some code, and matrix multiplication.

    $50 (Avg Bid)
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    7 入札