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    1,770 need project fpga freelance 仕事が見つかりました。次の価格: USD

    I have 50 skills that need Short SEO Headers. Example skill: JavaScript Short SEO Header: The right JavaScript professional can take your website design to new levels. Example skill: Wix Short SEO Header: Hiring a Wix professional can bring a new level of exposure to your business. Just one sentence. Context is the advantage of hiring a professional

    $91 (Avg Bid)
    特集
    $91 平均入札額
    11 入札

    ...motherboard. A daughter card with an Zynq FPGA/processor will install on this motherboard, and the motherboard will install onto a DAC board. There is a development board for this daughter card already. So this motherboard will just be a stripped down version of the development board with only the features we need. And powered by different regulation.

    $1800 (Avg Bid)
    $1800 平均入札額
    18 入札
    Labview MyRIO2 3 日 left
    認証完了

    Hi All, I have a project for someone who is expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes

    $161 (Avg Bid)
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    2 入札

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $122 (Avg Bid)
    $122 平均入札額
    21 入札

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
    $16 / hr 平均入札額
    29 入札
    modify ccminer to work with fpga 12 時間 left
    認証完了

    I need someone to modify the ccminer software. So it can communicate with FPGAs instead GPUs. It needs to work with both usb and pcie. I'm not asking for algorithm programming, I'm not asking for bitstreams. Just modifying the mining app ccminer so it works with FPGAs.

    $657 (Avg Bid)
    $657 平均入札額
    12 入札

    Hi guys, I...done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    $19 (Avg Bid)
    $19 平均入札額
    6 入札
    FPGA craze 終了 left

    coding of bitstreams, software licensing, imbedded commission

    $2372 (Avg Bid)
    $2372 平均入札額
    18 入札

    Hi All, I have a project for someone who is expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes

    $142 (Avg Bid)
    $142 平均入札額
    8 入札

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
    $33 平均入札額
    3 入札

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    $211 (Avg Bid)
    $211 平均入札額
    3 入札

    Hi All, I have a project for someone who is expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes

    $152 (Avg Bid)
    $152 平均入札額
    4 入札

    ...trying to make a project but I haven't purchased a board yet because I'm not sure which board to buy. So far, I've looked at the Zybo-Z7 or Arty-Z7. You will need to have these boards already obviously to complete this project. They both have sample projects for HDMI in and HDMI out. What I'm trying to accomplish is have: 1) PC->HDMI->FPGA...

    $361 (Avg Bid)
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    7 入札

    We are looking for DSP Firmware Engineer who has specialized in algorithms' performance optimization for DSP/FPGA based on VLIW architecture.

    $10 / hr (Avg Bid)
    $10 / hr 平均入札額
    2 入札
    Video converter 終了 left

    I am looking to create hardware that will convert HDMI to NDI (Network Device Interface) I need both hardware and [ログインしてURLを表示] is no set date when I need this by but would like it soon. There is an sdk for the conversion by fpga.

    $1361 (Avg Bid)
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    4 入札

    ...sent out of the FPGA chip through a single pin... Part 2 ...The serial transmission from part 1 is captured and converted to parallel data before being stored in another memory location( as 16 locations of 8-bits). The data in this memory should match with the data in memory in Part 1. Both parts are to be implemented in the same FPGA ....The serial

    $151 (Avg Bid)
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    I am building a tech blog about FPGA crypto mining. I need someone able to write tech articles, based on my request, about FPGA crypto mining. This is NOT something you can search on google and learn and write. Requirements: 1) You MUST have VERY GOOD knowledge about FPGAs 2) You MUST have VERY GOOD knowledge about crypto mining 3) You MUST be english/american

    $86 (Avg Bid)
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    17 入札

    I have a DE1-SoC FPGA board. I need an image build with a Linux installation (doesn't really matter) and the linux-socfpga kernel; however, the device tree blob on the installation must recognize the onboard FPGA peripherals, especially the onboard ADC. The goal is to have a working Linux image file, which when burned to an SD card would load Linux

    $149 (Avg Bid)
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    6 入札
    Read data sensor 終了 left

    Read data of sensor on FPGA Xillinx. More details via messenger Freelancer.com with full requirements.

    $138 (Avg Bid)
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    16 入札

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $176 (Avg Bid)
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    12 入札

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $149 (Avg Bid)
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    4 入札

    Needs to hire 2 Freelancers We are looking for designer to design Video object tracking : 1- CPU, CUDA based or FPGA accelerated algorithm . 2- Multi-target Detection/ tracking . 3- Moving object detection . 4- High accuracy , auto scaling , occlusion recovering . 5- fixed camera or moving camera. 6- Image Stabilization . 7- Move on Move tracking

    $1250 (Avg Bid)
    $1250 平均入札額
    21 入札

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    $461 (Avg Bid)
    $461 平均入札額
    4 入札

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    $261 (Avg Bid)
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    2 入札

    We are looking for someone with engineering background, preferably knowledge in FPGA related stuff to translate some tehnical documents. Google translate is not acceptable.

    $60 (Avg Bid)
    $60 平均入札額
    26 入札

    Looking for a mentor in advanced FPGA development using Altera Max 10 FPGA board specifically.

    $19 / hr (Avg Bid)
    $19 / hr 平均入札額
    9 入札

    1. Identify a good value and properly sized CPLD/FPGA and toolset (toolset needs to be relatively easy to configure) to accommodate the required functionality. 2. Develop the CPLD/FPGA code. The device needs to take as inputs a set of states (from a microcontroller so either as an I2C command or as a 3 digital input code, along with 3 digital inputs

    $125 (Avg Bid)
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    17 入札

    I need a network of thermostats that send data over Power Line Communication to a router where it is then sent over Ethernet and stored on a server. I will need to have software to access and display the data in graph form. There are other components that I need that are not so detailed. I need consulting for the design and components to use for both

    $144 (Avg Bid)
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    PCB design 終了 left

    I need a simple PCB design. The PCB should be square or rectangular with maximum dimensions of 9.5 cm x 9.5 cm. The PCB should hold 5 of the following boards: [ログインしてURLを表示] There should be some minimal interconnection between the 5 boards (more details to be provided). The USB ports on each

    $397 (Avg Bid)
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    I am looking for Xilinx SDx OpenCL expert, who can convert github miner project into FPGA hex file in Xilinx SDx. Don't bid if you do not have experience.

    $4992 (Avg Bid)
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    8 入札
    FPGA Project 終了 left

    Reading of sensor via PMOD on FPGA Xillinx. More details via messenger Freelancer.com with full requirements.

    $157 (Avg Bid)
    $157 平均入札額
    3 入札

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $154 (Avg Bid)
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    7 入札

    Hello Freelancers! I have this project fixes for 1 hour from now. Budget up to $15usd for 1 hour work max! We have the attached 128*128 image, i just need some fixes and to run it and produce the new image after the median filter we pass it through microblaze FPGA in the c program. I specifucally want: 1. instead of arrays i want the resulting image

    $22 (Avg Bid)
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    2 入札

    Hello everybody, I want a simple median filter in c embedded through a micriblaze fFPGA. I have some part of the code ready. i need it in 1 hour. If you got it lets talk :)

    $20 (Avg Bid)
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    1 入札

    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

    $10 (Avg Bid)
    $10 平均入札額
    1 入札

    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

    $10 (Avg Bid)
    $10 平均入札額
    1 入札

    Hello Dear, I have an urgent quick project. I have an embedded median filter of a table image 128*128 in c. I have the c code ready already. I just need you to take the median image 8*8 a nd pass it through FPGA with and without cache memory and then deliver the new images we get. It is for today please reply if interested

    $10 (Avg Bid)
    $10 平均入札額
    1 入札

    Hello Freelancers, I would like to pass my table image through a FPGA microblaze (both with cache and without cache) and have a s deliverables the 2 new images we get as results. This is for TODAY. Thank you in advance :)

    $10 - $30
    $10 - $30
    0 入札

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image

    $10 (Avg Bid)
    $10 平均入札額
    1 入札

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image

    $111 (Avg Bid)
    $111 平均入札額
    1 入札

    Hello guys I will need these simple tasks for $10 - $15 USD the first until today 8 September the second until tommorow 9 September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would comments on the code and the resulting image as deliverables

    $25 (Avg Bid)
    $25 平均入札額
    2 入札

    Hello guys I will need these simple tasks for $10 - $15 USD until 6 or 7 of September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach

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    3 入札

    ...fields so i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers

    $38 (Avg Bid)
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    111 入札

    ...working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the clock frequency is correct. Can you please help me , i need go deliver the project...

    $58 (Avg Bid)
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    1 入札

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
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    7 入札

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    $2830 (Avg Bid)
    $2830 平均入札額
    15 入札

    ...site. x.25. Electronics Radio Circuits designing and Radio Frequency transmitters and receiver data communication experience required, preferably in Meteor burst technology. FPGA, Microcontroller interfacing, Motorola VHF transceiver experience preferred. The main Aim is Data communication through wireless communication link x.25. VHF Meteor burst transmitter

    $5742 (Avg Bid)
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    11 入札

    ...Testing Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer

    $97 (Avg Bid)
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    16 入札

    ...task estimations and time tracking. • Understanding digital electronics and ability to read schematics, analog electronics is a big plus but not obligatory • Experience with FPGA is an asset • Understanding blue prints, engineering drawings and familiarity with PCBs • Experience with measurement instruments (multimeter, oscilloscope). Basic soldering

    $22 / hr (Avg Bid)
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    15 入札

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    $101 (Avg Bid)
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    2 入札