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    2,128 fpga 仕事が見つかりました。次の価格: USD

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

    $118 (Avg Bid)
    $118 平均入札額
    8 入札

    We have a Quartus software license and two Arria 10 boards (Terasic Han Platform). We want to give video input to one of the FPGAs through USB-C port and transmit it to the other board with one or multiple serial lines. At the other board, we want to get this video as output from the USB-C port again. We have XTS-FMC Boards for connection between the two FPGAs. We need a highly experienced FPGA ...

    $1108 (Avg Bid)
    $1108 平均入札額
    13 入札

    About us All-in-one solution for market data, order interface, order management and risk controls – at FPGA network card Level. Support for multiple trading applications using a single interface to the exchange, yet providing individual view of the order books for each application. Many solutions that are currently available either crunch the speed tests or concentrate on functionality...

    $633 (Avg Bid)
    地方
    $633 平均入札額
    3 入札

    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

    $27 (Avg Bid)
    $27 平均入札額
    2 入札

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

    $39 / hr (Avg Bid)
    $39 / hr 平均入札額
    19 入札

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $50 (Avg Bid)
    $50 平均入札額
    5 入札
    FPGA Engineer 18 時間 left
    認証完了

    For a Software Defined Radio module we are looking for a senior FPGA engineer. - Process all received data - Filter data for results - Etcetera To process and filter the data on the modules and possible FPGA within a specific SDR device. You will work with persons out of our team. You solve and test the issues they implement. Budget $800

    $969 (Avg Bid)
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    14 入札
    BladeRF (Software Defined Radio) 18 時間 left
    認証完了

    BladeRF specialist is needed that has experience with SDR (Software Defined Radio). We would like to set certain functions in the BladeRF: - Receiver (capture data) - Transmitter (page request) - Process all received data - Filter data for results - Multi bands simultaneously - Software define directional radio/antennas - Software define reach/width radio/antennas - Etcetera Require solution to ...

    $908 (Avg Bid)
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    9 入札
    Eye pupil tracking 17 時間 left

    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

    $70 (Avg Bid)
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    2 入札
    Program a project 14 時間 left

    I am a worker for a software company. I am currently using Altera DE2-115 FPGA board to configure it using Quartus software. We have to use NIOS II processor, QSYS, and Eclipse to write a program and to run the board. I am seeking some help in building this mini thing.

    $17 / hr (Avg Bid)
    $17 / hr 平均入札額
    14 入札

    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

    $22 (Avg Bid)
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    9 入札

    An expert on FPGA Board should bid only, showing a sample work will be an advantages

    $235 (Avg Bid)
    $235 平均入札額
    8 入札

    I am looking for electronic engineers having expertise in different microcontrollers like FPGA, Raspberry Pi, Arduino, PIC, ESP and many others having expertise in programming. I will share details of projects in chat

    $21 (Avg Bid)
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    19 入札

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

    $12 / hr (Avg Bid)
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    25 入札

    We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print.

    $132 (Avg Bid)
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    20 入札

    we need expierenced partner to build fpga mining software

    $20 / hr (Avg Bid)
    $20 / hr 平均入札額
    11 入札

    Please read carefully. You need to fix my code. I will sent to you in messages my project. Here is project description: The brightness measurement with help of PMODALS sensor ([ログインしてURLを表示] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([ログインしてURLを表示]) is to be used, which takes over the control. The result of the bright...

    $522 (Avg Bid)
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    14 入札
    FPGA Board 終了 left

    An expert on FPGA Board should bid only, showing a sample work will be an advantages

    $72 (Avg Bid)
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    12 入札

    Need expert labview for fpga control of an instrument

    $50 / hr (Avg Bid)
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    5 入札
    $178 平均入札額
    6 入札

    first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PCB of the board you have. U3 is ...

    $336 (Avg Bid)
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    5 入札

    Im looking for personnel to work on FPGA program in Singapore ,must be able to read current program or create an new program as required .Any one interested please contact me

    $330 (Avg Bid)
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    15 入札

    I need a line scan CMOS sensor (pixel size 14 micron X 200 microns) capable of line scan at a rate of 80KHz and output the data through ethernet to Xilinx FPGA.

    $523 (Avg Bid)
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    4 入札

    Hello, We are looking for a FPGA electric engineer who can help us engineer a FPGA board, customize an existing board. Preferable who can also develop in Python and C to connect the FPGA board with a RaspberryPi, and develop programs on both boards. You will receive project information later.

    $1154 (Avg Bid)
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    25 入札

    Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The brightness measurement with help of PMODALS sensor ([ログインしてURLを表示] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([ログインしてURLを表示]) is to be used, which takes over the control. The result of the brightn...

    $221 (Avg Bid)
    $221 平均入札額
    1 入札

    First task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop The second part of the project task is to populate the ADC and final amplifier stages on the PMU PCB, together with power...

    $200 (Avg Bid)
    $200 平均入札額
    4 入札

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $316 (Avg Bid)
    $316 平均入札額
    8 入札

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
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    1 入札

    We are looking at scanning,capturing and decoding multiple cellular frequencies(European 2G/3G/4G(LTE) bands) with an SDR. Currently using a simple rtl-sdr for this case but seeing as it lacks the frequency range(max 1800mhz) and has very little bandwidth(2.4MHz) we would like to upgrade to a better SDR. The goal is to analyze multiple simultaneous communication channels in real time. We are loo...

    $1489 (Avg Bid)
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    5 入札
    PCB Design 終了 left

    Use the xtal oscillator board that I designed and that works together with the FPGA to read the GPS data and then synchronise the 40 MHZ Voltage controlled Xtal oscillator to the 1 second pulse produced by the GPS. I will provide more details on chat.

    $156 (Avg Bid)
    $156 平均入札額
    18 入札

    I am looking for an expert in FPGA, its not a simple task, only expert place bids. will share details in chat

    $20 (Avg Bid)
    $20 平均入札額
    7 入札

    Need someone who has the PLDa PCIe ipcore license for Xilinx Vivado to help compile a FPGA project. I'll give you the source code. You compile and give me the bit file and compiled project.

    $207 (Avg Bid)
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    7 入札

    The test program used for transmited data between DDR4 of FPGA and DDR4 of PC adopted windows 10 or win7 system via PCIe 3.0 x8. A tested result shows that the speed of PCIE3.0 *8 is over 7GB/s , which is tested by xilinx Kcu1500 FPGA board. However, the speed under win7 / win10 is only about 4.5-4.9GB/s. The minimum speed threshold should be 5.5 GB/s. And it will be helpful if the speed...

    $7915 (Avg Bid)
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    5 入札

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

    $109 (Avg Bid)
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    6 入札

    i have projects related to all of these micro-controllers: Raspberry Pi FPGA PIC microcontroller STM microcontroller so looking for experts who can assist me with these projects

    $65 (Avg Bid)
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    18 入札

    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

    $103 (Avg Bid)
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    6 入札

    I want to make this tool by updating the hardware to a new fpga board, here is source code and some documents about it. [ログインしてURLを表示]:projects:smartlogic [ログインしてURLを表示] [ログインしてURLを表示]

    $506 (Avg Bid)
    $506 平均入札額
    12 入札

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

    $103 (Avg Bid)
    $103 平均入札額
    15 入札

    PANEL = Artix-7 100t - ERROR: [Labtools 27-2269] Hi, I am facing ERROR: [Labtools 27-2269] after issueing the open_hw_target command. Vivado 2019.1 Windows 10 Connected through micro USB for serial communication. MODE = JTAG Any suggestion as to how can i detect the devide to burn my bitstream for execution? Thanks!!

    $55 (Avg Bid)
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    1 入札

    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

    $222 (Avg Bid)
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    10 入札

    Using LabVIEW, FPGA & RT softwares, I need a data logger with cRIO-9047 chases for following modules. 1) 9205 2)9237 3)9232 4)9361 5)9467 I want to log data in RT (FPGA) at 10Khz for no more than 3 minutes. Two Load Cells, One Accelerometer, linear displacement through encoder, Trigger input by some switch, Speed tracking. After recording data I want to analyse it specially Accelerometer dat...

    $665 (Avg Bid)
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    17 入札
    $15 平均入札額
    8 入札
    i need a coder 終了 left

    FPGA Bode Designer for Real-time application

    $1539 (Avg Bid)
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    5 入札
    $23 平均入札額
    19 入札

    simple fpga addition subtraction code

    $22 (Avg Bid)
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    14 入札

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